On Wed, 24 May 2023, Dmitry Vyukov <dvyu...@google.com> wrote: > On Tue, 23 May 2023 at 18:05, Olivier Dion <od...@efficios.com> wrote:
> I don't this this is true in the C/C++ memory model: > "the preceding atomic exchange with sequential consistency already > acts as an implicit release (in term of memory barrier) for the > following store". > > std::atomic_thread_fence does affect all preceding/subsequent > operations, but an atomic memory operation only affects ordering on > that variable, it doesn't also serve as a standalone memory fence. After reading the standard, we concur with you. We had to revisit the memory model used by URCU to understand the conflict. While doing so, we had to adapt some of the algorithms that were assuming implicit full memory barriers with operation such as CAS. Thank for the insight! -- Olivier Dion EfficiOS Inc. https://www.efficios.com _______________________________________________ lttng-dev mailing list lttng-dev@lists.lttng.org https://lists.lttng.org/cgi-bin/mailman/listinfo/lttng-dev
