Author: lattner
Date: Mon Dec 31 21:07:29 2007
New Revision: 45480
URL: http://llvm.org/viewvc/llvm-project?rev=45480&view=rev
Log:
Add a trivial but handy function to efficiently return the machine
instruction that defines the specified vreg. Crazy.
Modified:
llvm/trunk/include/llvm/CodeGen/MachineRegisterInfo.h
llvm/trunk/lib/CodeGen/MachineRegisterInfo.cpp
Modified: llvm/trunk/include/llvm/CodeGen/MachineRegisterInfo.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineRegisterInfo.h?rev=45480&r1=45479&r2=45480&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/MachineRegisterInfo.h (original)
+++ llvm/trunk/include/llvm/CodeGen/MachineRegisterInfo.h Mon Dec 31 21:07:29
2007
@@ -120,6 +120,12 @@
return VRegInfo.size()+MRegisterInfo::FirstVirtualRegister-1;
}
+ /// getVRegDef - Return the machine instr that defines the specified virtual
+ /// register or null if none is found. This assumes that the code is in SSA
+ /// form, so there should only be one definition.
+ MachineInstr *getVRegDef(unsigned Reg) const;
+
+
//===--------------------------------------------------------------------===//
// Physical Register Use Info
//===--------------------------------------------------------------------===//
Modified: llvm/trunk/lib/CodeGen/MachineRegisterInfo.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineRegisterInfo.cpp?rev=45480&r1=45479&r2=45480&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineRegisterInfo.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineRegisterInfo.cpp Mon Dec 31 21:07:29 2007
@@ -44,3 +44,18 @@
List->Contents.Reg.Prev = &VRegInfo[i].second;
}
}
+
+
+/// getVRegDef - Return the machine instr that defines the specified virtual
+/// register or null if none is found. This assumes that the code is in SSA
+/// form, so there should only be one definition.
+MachineInstr *MachineRegisterInfo::getVRegDef(unsigned Reg) const {
+ assert(Reg-MRegisterInfo::FirstVirtualRegister < VRegInfo.size() &&
+ "Invalid vreg!");
+ for (reg_iterator I = reg_begin(Reg), E = reg_end(); I != E; ++I) {
+ // Since we are in SSA form, we can stop at the first definition.
+ if (I->isDef())
+ return I->getParent();
+ }
+ return 0;
+}
_______________________________________________
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
