>> It seems that simple remat works for things that: >> >> 1. have no side effects >> 2. have no register inputs >> >> Is there another condition? > > Can't think of any. > >> >> If so, simple remat can check #2 today, just by itself looking at the >> machineinstr. Given that, it comes down to how we want to >> represent #1. > > I don't see a better way so I guess this will be a targetinstrinfo > bit (true for those with side-effects).
Okay, the tricky thing here is instructions that have "conditional side effects". For example, all instructions marked isload/isstore/ iscall etc should be considered to have side effects (as would anything with implicit definitions), but loads from constant pools and other special cases should not be considered to have side effects. This sounds like the exact same class of problems we already have with trivial remat :) -Chris _______________________________________________ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
