> We can eliminate LDRcp, that's fine.
>
> However, I still don't like the separate hook and targetinstrinfo
> bit. Dan, can you have just a single isTriviallyReMaterializable hook
> that encompass all these?
What do you think about the attached patch? It's not tested yet, but it
shows what I think you're asking for. I left LDRcp in, but that can be fixed.
Dan
--
Dan Gohman, Cray Inc.
Index: include/llvm/Target/TargetInstrInfo.h
===================================================================
RCS file: /var/cvs/llvm/llvm/include/llvm/Target/TargetInstrInfo.h,v
retrieving revision 1.130
diff -u -r1.130 TargetInstrInfo.h
--- include/llvm/Target/TargetInstrInfo.h 15 Jun 2007 21:13:54 -0000
1.130
+++ include/llvm/Target/TargetInstrInfo.h 18 Jun 2007 21:17:17 -0000
@@ -78,10 +78,6 @@
// controls execution. It may be set to 'always'.
const unsigned M_PREDICABLE = 1 << 12;
-// M_REMATERIALIZIBLE - Set if this instruction can be trivally re-materialized
-// at any time, e.g. constant generation, load from constant pool.
-const unsigned M_REMATERIALIZIBLE = 1 << 13;
-
// M_CLOBBERS_PRED - Set if this instruction may clobbers the condition code
// register and / or registers that are used to predicate instructions.
const unsigned M_CLOBBERS_PRED = 1 << 14;
@@ -217,9 +213,6 @@
bool clobbersPredicate(MachineOpCode Opcode) const {
return get(Opcode).Flags & M_CLOBBERS_PRED;
}
- bool isReMaterializable(MachineOpCode Opcode) const {
- return get(Opcode).Flags & M_REMATERIALIZIBLE;
- }
bool isCommutableInstr(MachineOpCode Opcode) const {
return get(Opcode).Flags & M_COMMUTABLE;
}
@@ -298,13 +291,13 @@
return 0;
}
- /// isOtherReMaterializableLoad - If the specified machine instruction is a
- /// direct load that is trivially rematerializable, not counting loads from
- /// stack slots, return true. If not, return false. This predicate must
+ /// isTriviallyReMaterializable - If the specified machine instruction can
+ /// be trivally re-materialized at any time, e.g. constant generation or
+ /// loads from constant pools. If not, return false. This predicate must
/// return false if the instruction has any side effects other than
/// producing the value from the load, or if it requres any address
/// registers that are not always available.
- virtual bool isOtherReMaterializableLoad(MachineInstr *MI) const {
+ virtual bool isTriviallyReMaterializable(MachineInstr *MI) const {
return false;
}
Index: lib/CodeGen/LiveIntervalAnalysis.cpp
===================================================================
RCS file: /var/cvs/llvm/llvm/lib/CodeGen/LiveIntervalAnalysis.cpp,v
retrieving revision 1.247
diff -u -r1.247 LiveIntervalAnalysis.cpp
--- lib/CodeGen/LiveIntervalAnalysis.cpp 14 Jun 2007 20:50:44 -0000
1.247
+++ lib/CodeGen/LiveIntervalAnalysis.cpp 18 Jun 2007 21:17:17 -0000
@@ -336,14 +336,13 @@
// time we see a vreg.
if (interval.empty()) {
// Remember if the definition can be rematerialized. All load's from fixed
- // stack slots are re-materializable. The target may permit other loads to
- // be re-materialized as well.
+ // stack slots are re-materializable. The target may permit other
+ // instructions to be re-materialized as well.
int FrameIdx = 0;
if (vi.DefInst &&
- (tii_->isReMaterializable(vi.DefInst->getOpcode()) ||
+ (tii_->isTriviallyReMaterializable(vi.DefInst) ||
(tii_->isLoadFromStackSlot(vi.DefInst, FrameIdx) &&
- mf_->getFrameInfo()->isFixedObjectIndex(FrameIdx)) ||
- tii_->isOtherReMaterializableLoad(vi.DefInst)))
+ mf_->getFrameInfo()->isFixedObjectIndex(FrameIdx))))
interval.remat = vi.DefInst;
// Get the Idx of the defining instructions.
Index: lib/CodeGen/VirtRegMap.cpp
===================================================================
RCS file: /var/cvs/llvm/llvm/lib/CodeGen/VirtRegMap.cpp,v
retrieving revision 1.112
diff -u -r1.112 VirtRegMap.cpp
--- lib/CodeGen/VirtRegMap.cpp 14 Jun 2007 20:50:44 -0000 1.112
+++ lib/CodeGen/VirtRegMap.cpp 18 Jun 2007 21:17:17 -0000
@@ -663,9 +663,8 @@
// If this instruction is being rematerialized, just remove it!
int FrameIdx;
- if ((TID->Flags & M_REMATERIALIZIBLE) ||
- TII->isLoadFromStackSlot(&MI, FrameIdx) ||
- TII->isOtherReMaterializableLoad(&MI)) {
+ if (TII->isTriviallyReMaterializable(&MI) ||
+ TII->isLoadFromStackSlot(&MI, FrameIdx)) {
bool Remove = true;
for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
MachineOperand &MO = MI.getOperand(i);
Index: lib/Target/Target.td
===================================================================
RCS file: /var/cvs/llvm/llvm/lib/Target/Target.td,v
retrieving revision 1.103
diff -u -r1.103 Target.td
--- lib/Target/Target.td 13 Jun 2007 22:20:15 -0000 1.103
+++ lib/Target/Target.td 18 Jun 2007 21:17:17 -0000
@@ -186,7 +186,6 @@
bit isConvertibleToThreeAddress = 0; // Can this 2-addr instruction promote?
bit isCommutable = 0; // Is this 3 operand instruction commutable?
bit isTerminator = 0; // Is this part of the terminator for a basic
block?
- bit isReMaterializable = 0; // Is this instruction re-materializable?
bit isPredicable = 0; // Is this instruction predicable?
bit hasDelaySlot = 0; // Does this instruction have an delay slot?
bit usesCustomDAGSchedInserter = 0; // Pseudo instr needing special help.
Index: lib/Target/ARM/ARMInstrInfo.cpp
===================================================================
RCS file: /var/cvs/llvm/llvm/lib/Target/ARM/ARMInstrInfo.cpp,v
retrieving revision 1.37
diff -u -r1.37 ARMInstrInfo.cpp
--- lib/Target/ARM/ARMInstrInfo.cpp 15 Jun 2007 21:15:00 -0000 1.37
+++ lib/Target/ARM/ARMInstrInfo.cpp 18 Jun 2007 21:17:17 -0000
@@ -130,6 +130,20 @@
return 0;
}
+bool ARMInstrInfo::isTriviallyReMaterializable(MachineInstr *MI) const {
+ switch (MI->getOpcode()) {
+ default: break;
+ case ARM::LDRcp:
+ case ARM::MOVi:
+ case ARM::MVNi:
+ case ARM::MOVi2pieces:
+ case ARM::tLDRcp:
+ // These instructions are always trivially rematerializable.
+ return true;
+ }
+ return false;
+}
+
static unsigned getUnindexedOpcode(unsigned Opc) {
switch (Opc) {
default: break;
Index: lib/Target/ARM/ARMInstrInfo.h
===================================================================
RCS file: /var/cvs/llvm/llvm/lib/Target/ARM/ARMInstrInfo.h,v
retrieving revision 1.14
diff -u -r1.14 ARMInstrInfo.h
--- lib/Target/ARM/ARMInstrInfo.h 15 Jun 2007 21:15:00 -0000 1.14
+++ lib/Target/ARM/ARMInstrInfo.h 18 Jun 2007 21:17:17 -0000
@@ -87,6 +87,7 @@
unsigned &SrcReg, unsigned &DstReg) const;
virtual unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex)
const;
virtual unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const;
+ virtual bool isTriviallyReMaterializable(MachineInstr *MI) const;
virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
MachineBasicBlock::iterator
&MBBI,
Index: lib/Target/ARM/ARMInstrInfo.td
===================================================================
RCS file: /var/cvs/llvm/llvm/lib/Target/ARM/ARMInstrInfo.td,v
retrieving revision 1.110
diff -u -r1.110 ARMInstrInfo.td
--- lib/Target/ARM/ARMInstrInfo.td 6 Jun 2007 10:17:05 -0000 1.110
+++ lib/Target/ARM/ARMInstrInfo.td 18 Jun 2007 21:17:17 -0000
@@ -665,7 +665,6 @@
[(set GPR:$dst, (load addrmode2:$addr))]>;
// Special LDR for loads from non-pc-relative constpools.
-let isReMaterializable = 1 in
def LDRcp : AI2<(ops GPR:$dst, addrmode2:$addr),
"ldr", " $dst, $addr", []>;
@@ -799,7 +798,6 @@
def MOVs : AI1<(ops GPR:$dst, so_reg:$src),
"mov", " $dst, $src", [(set GPR:$dst, so_reg:$src)]>;
-let isReMaterializable = 1 in
def MOVi : AI1<(ops GPR:$dst, so_imm:$src),
"mov", " $dst, $src", [(set GPR:$dst, so_imm:$src)]>;
@@ -907,7 +905,6 @@
"mvn", " $dst, $src", [(set GPR:$dst, (not GPR:$src))]>;
def MVNs : AI<(ops GPR:$dst, so_reg:$src),
"mvn", " $dst, $src", [(set GPR:$dst, (not so_reg:$src))]>;
-let isReMaterializable = 1 in
def MVNi : AI<(ops GPR:$dst, so_imm:$imm),
"mvn", " $dst, $imm", [(set GPR:$dst, so_imm_not:$imm)]>;
@@ -1177,7 +1174,6 @@
// Large immediate handling.
// Two piece so_imms.
-let isReMaterializable = 1 in
def MOVi2pieces : AI1x2<(ops GPR:$dst, so_imm2part:$src),
"mov", " $dst, $src",
[(set GPR:$dst, so_imm2part:$src)]>;
Index: lib/Target/ARM/ARMInstrThumb.td
===================================================================
RCS file: /var/cvs/llvm/llvm/lib/Target/ARM/ARMInstrThumb.td,v
retrieving revision 1.30
diff -u -r1.30 ARMInstrThumb.td
--- lib/Target/ARM/ARMInstrThumb.td 8 Jun 2007 09:13:23 -0000 1.30
+++ lib/Target/ARM/ARMInstrThumb.td 18 Jun 2007 21:17:17 -0000
@@ -266,7 +266,6 @@
[(set GPR:$dst, (load (ARMWrapper tconstpool:$addr)))]>;
// Special LDR for loads from non-pc-relative constpools.
-let isReMaterializable = 1 in
def tLDRcp : TIs<(ops GPR:$dst, i32imm:$addr),
"ldr $dst, $addr", []>;
} // isLoad
Index: lib/Target/X86/X86InstrFPStack.td
===================================================================
RCS file: /var/cvs/llvm/llvm/lib/Target/X86/X86InstrFPStack.td,v
retrieving revision 1.9
diff -u -r1.9 X86InstrFPStack.td
--- lib/Target/X86/X86InstrFPStack.td 21 Mar 2007 00:16:56 -0000 1.9
+++ lib/Target/X86/X86InstrFPStack.td 18 Jun 2007 21:17:17 -0000
@@ -413,12 +413,10 @@
def FXCH : FPI<0xC8, AddRegFrm, (ops RST:$op), "fxch $op">, D9;
// Floating point constant loads.
-let isReMaterializable = 1 in {
def FpLD0 : FpI<(ops RFP:$dst), ZeroArgFP,
[(set RFP:$dst, fp64imm0)]>;
def FpLD1 : FpI<(ops RFP:$dst), ZeroArgFP,
[(set RFP:$dst, fp64imm1)]>;
-}
def FLD0 : FPI<0xEE, RawFrm, (ops), "fldz">, D9;
def FLD1 : FPI<0xE8, RawFrm, (ops), "fld1">, D9;
Index: lib/Target/X86/X86InstrInfo.cpp
===================================================================
RCS file: /var/cvs/llvm/llvm/lib/Target/X86/X86InstrInfo.cpp,v
retrieving revision 1.91
diff -u -r1.91 X86InstrInfo.cpp
--- lib/Target/X86/X86InstrInfo.cpp 14 Jun 2007 22:03:45 -0000 1.91
+++ lib/Target/X86/X86InstrInfo.cpp 18 Jun 2007 21:17:17 -0000
@@ -112,9 +112,20 @@
}
-bool X86InstrInfo::isOtherReMaterializableLoad(MachineInstr *MI) const {
+bool X86InstrInfo::isTriviallyReMaterializable(MachineInstr *MI) const {
switch (MI->getOpcode()) {
default: break;
+ case X86::FpLD0:
+ case X86::FpLD1:
+ case X86::MOV8ri:
+ case X86::MOV16ri:
+ case X86::MOV32ri:
+ case X86::MMX_V_SET0:
+ case X86::MMX_V_SETALLONES:
+ case X86::V_SET0:
+ case X86::V_SETALLONES:
+ // These instructions are always trivially rematerializable.
+ return true;
case X86::MOV8rm:
case X86::MOV16rm:
case X86::MOV16_rm:
@@ -128,6 +139,7 @@
case X86::MOVAPDrm:
case X86::MMX_MOVD64rm:
case X86::MMX_MOVQ64rm:
+ // Loads from constant pools are trivially rematerializable.
return MI->getOperand(1).isRegister() && MI->getOperand(2).isImmediate() &&
MI->getOperand(3).isRegister() &&
MI->getOperand(4).isConstantPoolIndex() &&
MI->getOperand(1).getReg() == 0 &&
Index: lib/Target/X86/X86InstrInfo.h
===================================================================
RCS file: /var/cvs/llvm/llvm/lib/Target/X86/X86InstrInfo.h,v
retrieving revision 1.66
diff -u -r1.66 X86InstrInfo.h
--- lib/Target/X86/X86InstrInfo.h 14 Jun 2007 22:03:45 -0000 1.66
+++ lib/Target/X86/X86InstrInfo.h 18 Jun 2007 21:17:17 -0000
@@ -239,7 +239,7 @@
unsigned& destReg) const;
unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const;
unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const;
- bool isOtherReMaterializableLoad(MachineInstr *MI) const;
+ bool isTriviallyReMaterializable(MachineInstr *MI) const;
/// convertToThreeAddress - This method must be implemented by targets that
/// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
Index: lib/Target/X86/X86InstrInfo.td
===================================================================
RCS file: /var/cvs/llvm/llvm/lib/Target/X86/X86InstrInfo.td,v
retrieving revision 1.307
diff -u -r1.307 X86InstrInfo.td
--- lib/Target/X86/X86InstrInfo.td 6 May 2007 04:00:55 -0000 1.307
+++ lib/Target/X86/X86InstrInfo.td 18 Jun 2007 21:17:17 -0000
@@ -617,7 +617,6 @@
"mov{w} {$src, $dst|$dst, $src}", []>, OpSize;
def MOV32rr : I<0x89, MRMDestReg, (ops GR32:$dst, GR32:$src),
"mov{l} {$src, $dst|$dst, $src}", []>;
-let isReMaterializable = 1 in {
def MOV8ri : Ii8 <0xB0, AddRegFrm, (ops GR8 :$dst, i8imm :$src),
"mov{b} {$src, $dst|$dst, $src}",
[(set GR8:$dst, imm:$src)]>;
@@ -627,7 +626,6 @@
def MOV32ri : Ii32<0xB8, AddRegFrm, (ops GR32:$dst, i32imm:$src),
"mov{l} {$src, $dst|$dst, $src}",
[(set GR32:$dst, imm:$src)]>;
-}
def MOV8mi : Ii8 <0xC6, MRM0m, (ops i8mem :$dst, i8imm :$src),
"mov{b} {$src, $dst|$dst, $src}",
[(store (i8 imm:$src), addr:$dst)]>;
Index: lib/Target/X86/X86InstrMMX.td
===================================================================
RCS file: /var/cvs/llvm/llvm/lib/Target/X86/X86InstrMMX.td,v
retrieving revision 1.32
diff -u -r1.32 X86InstrMMX.td
--- lib/Target/X86/X86InstrMMX.td 16 May 2007 06:08:17 -0000 1.32
+++ lib/Target/X86/X86InstrMMX.td 18 Jun 2007 21:17:18 -0000
@@ -503,14 +503,12 @@
// Alias instructions that map zero vector to pxor.
// FIXME: remove when we can teach regalloc that xor reg, reg is ok.
-let isReMaterializable = 1 in {
- def MMX_V_SET0 : MMXI<0xEF, MRMInitReg, (ops VR64:$dst),
- "pxor $dst, $dst",
- [(set VR64:$dst, (v1i64 immAllZerosV))]>;
- def MMX_V_SETALLONES : MMXI<0x76, MRMInitReg, (ops VR64:$dst),
- "pcmpeqd $dst, $dst",
- [(set VR64:$dst, (v1i64 immAllOnesV))]>;
-}
+def MMX_V_SET0 : MMXI<0xEF, MRMInitReg, (ops VR64:$dst),
+ "pxor $dst, $dst",
+ [(set VR64:$dst, (v1i64 immAllZerosV))]>;
+def MMX_V_SETALLONES : MMXI<0x76, MRMInitReg, (ops VR64:$dst),
+ "pcmpeqd $dst, $dst",
+ [(set VR64:$dst, (v1i64 immAllOnesV))]>;
//===----------------------------------------------------------------------===//
// Non-Instruction Patterns
Index: lib/Target/X86/X86InstrSSE.td
===================================================================
RCS file: /var/cvs/llvm/llvm/lib/Target/X86/X86InstrSSE.td,v
retrieving revision 1.183
diff -u -r1.183 X86InstrSSE.td
--- lib/Target/X86/X86InstrSSE.td 17 May 2007 18:44:37 -0000 1.183
+++ lib/Target/X86/X86InstrSSE.td 18 Jun 2007 21:17:18 -0000
@@ -759,7 +759,6 @@
// Alias instructions that map zero vector to pxor / xorp* for sse.
// FIXME: remove when we can teach regalloc that xor reg, reg is ok.
-let isReMaterializable = 1 in
def V_SET0 : PSI<0x57, MRMInitReg, (ops VR128:$dst),
"xorps $dst, $dst",
[(set VR128:$dst, (v4f32 immAllZerosV))]>;
@@ -1819,10 +1818,9 @@
// Alias instructions that map zero vector to pxor / xorp* for sse.
// FIXME: remove when we can teach regalloc that xor reg, reg is ok.
-let isReMaterializable = 1 in
- def V_SETALLONES : PDI<0x76, MRMInitReg, (ops VR128:$dst),
- "pcmpeqd $dst, $dst",
- [(set VR128:$dst, (v2f64 immAllOnesV))]>;
+def V_SETALLONES : PDI<0x76, MRMInitReg, (ops VR128:$dst),
+ "pcmpeqd $dst, $dst",
+ [(set VR128:$dst, (v2f64 immAllOnesV))]>;
// FR64 to 128-bit vector conversion.
def MOVSD2PDrr : SDI<0x10, MRMSrcReg, (ops VR128:$dst, FR64:$src),
Index: utils/TableGen/CodeGenInstruction.h
===================================================================
RCS file: /var/cvs/llvm/llvm/utils/TableGen/CodeGenInstruction.h,v
retrieving revision 1.28
diff -u -r1.28 CodeGenInstruction.h
--- utils/TableGen/CodeGenInstruction.h 6 Jun 2007 10:14:55 -0000 1.28
+++ utils/TableGen/CodeGenInstruction.h 18 Jun 2007 21:17:21 -0000
@@ -91,7 +91,6 @@
bool isConvertibleToThreeAddress;
bool isCommutable;
bool isTerminator;
- bool isReMaterializable;
bool hasDelaySlot;
bool usesCustomDAGSchedInserter;
bool hasVariableNumberOfOperands;
Index: utils/TableGen/CodeGenTarget.cpp
===================================================================
RCS file: /var/cvs/llvm/llvm/utils/TableGen/CodeGenTarget.cpp,v
retrieving revision 1.92
diff -u -r1.92 CodeGenTarget.cpp
--- utils/TableGen/CodeGenTarget.cpp 13 Jun 2007 22:20:15 -0000 1.92
+++ utils/TableGen/CodeGenTarget.cpp 18 Jun 2007 21:17:21 -0000
@@ -365,7 +365,6 @@
isConvertibleToThreeAddress =
R->getValueAsBit("isConvertibleToThreeAddress");
isCommutable = R->getValueAsBit("isCommutable");
isTerminator = R->getValueAsBit("isTerminator");
- isReMaterializable = R->getValueAsBit("isReMaterializable");
hasDelaySlot = R->getValueAsBit("hasDelaySlot");
usesCustomDAGSchedInserter = R->getValueAsBit("usesCustomDAGSchedInserter");
hasCtrlDep = R->getValueAsBit("hasCtrlDep");
Index: utils/TableGen/InstrInfoEmitter.cpp
===================================================================
RCS file: /var/cvs/llvm/llvm/utils/TableGen/InstrInfoEmitter.cpp,v
retrieving revision 1.60
diff -u -r1.60 InstrInfoEmitter.cpp
--- utils/TableGen/InstrInfoEmitter.cpp 6 Jun 2007 10:14:55 -0000 1.60
+++ utils/TableGen/InstrInfoEmitter.cpp 18 Jun 2007 21:17:21 -0000
@@ -240,7 +240,6 @@
if (Inst.isConvertibleToThreeAddress) OS << "|M_CONVERTIBLE_TO_3_ADDR";
if (Inst.isCommutable) OS << "|M_COMMUTABLE";
if (Inst.isTerminator) OS << "|M_TERMINATOR_FLAG";
- if (Inst.isReMaterializable) OS << "|M_REMATERIALIZIBLE";
if (Inst.clobbersPred) OS << "|M_CLOBBERS_PRED";
if (Inst.usesCustomDAGSchedInserter)
OS << "|M_USES_CUSTOM_DAG_SCHED_INSERTION";
_______________________________________________
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
