[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp

[Chris Lattner]

Changes in directory llvm/lib/Target/X86:

X86ISelLowering.cpp updated: 1.407 -> 1.408
---
Log message:

fix x86-64 mmx calling convention for real, which passes in integer gprs.


---
Diffs of the changes:  (+9 -3)

 X86ISelLowering.cpp |   12 +++++++++---
 1 files changed, 9 insertions(+), 3 deletions(-)


Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.407 
llvm/lib/Target/X86/X86ISelLowering.cpp:1.408
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.407       Sat Jun  9 00:01:50 2007
+++ llvm/lib/Target/X86/X86ISelLowering.cpp     Sat Jun  9 00:08:10 2007
@@ -1183,9 +1183,10 @@
         RC = X86::FR64RegisterClass;
       else {
         assert(MVT::isVector(RegVT));
-        if (MVT::getSizeInBits(RegVT) == 64)
-          RC = X86::VR64RegisterClass;
-        else
+        if (MVT::getSizeInBits(RegVT) == 64) {
+          RC = X86::GR64RegisterClass;       // MMX values are passed in GPRs.
+          RegVT = MVT::i64;
+        } else
           RC = X86::VR128RegisterClass;
       }
 
@@ -1205,6 +1206,11 @@
       if (VA.getLocInfo() != CCValAssign::Full)
         ArgValue = DAG.getNode(ISD::TRUNCATE, VA.getValVT(), ArgValue);
       
+      // Handle MMX values passed in GPRs.
+      if (RegVT != VA.getLocVT() && RC == X86::GR64RegisterClass &&
+          MVT::getSizeInBits(RegVT) == 64)
+        ArgValue = DAG.getNode(ISD::BIT_CONVERT, VA.getLocVT(), ArgValue);
+      
       ArgValues.push_back(ArgValue);
     } else {
       assert(VA.isMemLoc());



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