Changes in directory llvm/lib/Target/ARM:
ARMInstrInfo.td updated: 1.102 -> 1.103
---
Log message:
Make ARM::B isPredicable; Make Bcc and MOVCC condition option a normal operand
so they are not predicable.
---
Diffs of the changes: (+6 -5)
ARMInstrInfo.td | 11 ++++++-----
1 files changed, 6 insertions(+), 5 deletions(-)
Index: llvm/lib/Target/ARM/ARMInstrInfo.td
diff -u llvm/lib/Target/ARM/ARMInstrInfo.td:1.102
llvm/lib/Target/ARM/ARMInstrInfo.td:1.103
--- llvm/lib/Target/ARM/ARMInstrInfo.td:1.102 Wed May 16 02:45:54 2007
+++ llvm/lib/Target/ARM/ARMInstrInfo.td Wed May 16 15:50:01 2007
@@ -278,7 +278,7 @@
}
// ARM branch / cmov condition code operand.
-def ccop : PredicateOperand<i32, (ops i32imm), (ops)> {
+def ccop : Operand<i32> {
let PrintMethod = "printPredicateOperand";
}
@@ -364,7 +364,7 @@
let Pattern = pattern;
}
-// Almost all ARM instructions are predicatable.
+// Almost all ARM instructions are predicable.
class I<dag oprnds, AddrMode am, SizeFlagVal sz, IndexMode im,
string opc, string asm, string cstr, list<dag> pattern>
// FIXME: Set all opcodes to 0 for now.
@@ -591,10 +591,11 @@
}
let isBranch = 1, isTerminator = 1, noResults = 1 in {
- // B can changed into a Bcc, but it is not "predicated".
+ // B is "predicable" since it can be xformed into a Bcc.
let isBarrier = 1 in {
- def B : AXI<(ops brtarget:$dst), "b $dst",
- [(br bb:$dst)]>;
+ let isPredicable = 1 in
+ def B : AXI<(ops brtarget:$dst), "b $dst",
+ [(br bb:$dst)]>;
def BR_JTr : JTI<(ops GPR:$dst, jtblock_operand:$jt, i32imm:$id),
"mov", " pc, $dst \n$jt",
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