> Implement the llvm.bit.part_select.iN.iN.iN overloaded intrinsic.
Urr? This is obviously incorrect. I'd much rather have the code
generator assert and die on an unsupported intrinsic than to
miscompile it silently.
-Chris
>
> ---
> Diffs of the changes: (+5 -0)
>
> SelectionDAGISel.cpp | 5 +++++
> 1 files changed, 5 insertions(+)
>
>
> Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
> diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.402
> llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.403
> --- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.402 Wed
> Apr 4 16:14:49 2007
> +++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Wed Apr 4
> 18:48:25 2007
> @@ -2438,6 +2438,11 @@
> DAG.setRoot(Tmp.getValue(1));
> return 0;
> }
> + case Intrinsic::bit_part_select: {
> + MVT::ValueType Ty = getValue(I.getOperand(1)).getValueType();
> + setValue(&I, DAG.getTargetConstant(0, Ty));
> + return 0;
> + }
> case Intrinsic::bswap:
> setValue(&I, DAG.getNode(ISD::BSWAP,
> getValue(I.getOperand(1)).getValueType
> (),
>
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits@cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
_______________________________________________
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
