Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAG.cpp updated: 1.101 -> 1.102
SelectionDAGISel.cpp updated: 1.271 -> 1.272
---
Log message:
Completely eliminate def&use operands. Now a register operand is EITHER a
def operand or a use operand.
---
Diffs of the changes: (+12 -12)
ScheduleDAG.cpp | 16 ++++++++--------
SelectionDAGISel.cpp | 8 ++++----
2 files changed, 12 insertions(+), 12 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.101
llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.102
--- llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.101 Wed Aug 16 19:09:56 2006
+++ llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp Mon Sep 4 21:31:13 2006
@@ -255,11 +255,11 @@
// the machine instruction.
unsigned ResultReg =
RegMap->createVirtualRegister(getInstrOperandRegClass(MRI, TII, &II, 0));
- MI->addRegOperand(ResultReg, MachineOperand::Def);
+ MI->addRegOperand(ResultReg, true);
for (unsigned i = 1; i != NumResults; ++i) {
const TargetRegisterClass *RC = getInstrOperandRegClass(MRI, TII, &II, i);
assert(RC && "Isn't a register operand!");
- MI->addRegOperand(RegMap->createVirtualRegister(RC), MachineOperand::Def);
+ MI->addRegOperand(RegMap->createVirtualRegister(RC), true);
}
return ResultReg;
}
@@ -291,7 +291,7 @@
// Get/emit the operand.
unsigned VReg = getVR(Op, VRBaseMap);
- MI->addRegOperand(VReg, MachineOperand::Use);
+ MI->addRegOperand(VReg, false);
// Verify that it is right.
assert(MRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
@@ -307,7 +307,7 @@
MI->addImmOperand(C->getValue());
} else if (RegisterSDNode*R =
dyn_cast<RegisterSDNode>(Op)) {
- MI->addRegOperand(R->getReg(), MachineOperand::Use);
+ MI->addRegOperand(R->getReg(), false);
} else if (GlobalAddressSDNode *TGA =
dyn_cast<GlobalAddressSDNode>(Op)) {
MI->addGlobalAddressOperand(TGA->getGlobal(), TGA->getOffset());
@@ -349,7 +349,7 @@
Op.getValueType() != MVT::Flag &&
"Chain and flag operands should occur at end of operand list!");
unsigned VReg = getVR(Op, VRBaseMap);
- MI->addRegOperand(VReg, MachineOperand::Use);
+ MI->addRegOperand(VReg, false);
// Verify that it is right.
assert(MRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
@@ -402,7 +402,7 @@
unsigned Reg = cast<RegisterSDNode>(Use->getOperand(1))->getReg();
if (MRegisterInfo::isVirtualRegister(Reg)) {
VRBase = Reg;
- MI->addRegOperand(Reg, MachineOperand::Def);
+ MI->addRegOperand(Reg, true);
break;
}
}
@@ -529,13 +529,13 @@
case 1: // Use of register.
for (; NumVals; --NumVals, ++i) {
unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
- MI->addRegOperand(Reg, MachineOperand::Use);
+ MI->addRegOperand(Reg, false);
}
break;
case 2: // Def of register.
for (; NumVals; --NumVals, ++i) {
unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
- MI->addRegOperand(Reg, MachineOperand::Def);
+ MI->addRegOperand(Reg, true);
}
break;
case 3: { // Immediate.
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.271
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.272
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.271 Sun Aug 27
07:54:01 2006
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Mon Sep 4 21:31:13 2006
@@ -3547,7 +3547,7 @@
MachineInstr *PHI = PHINodesToUpdate[i].first;
assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
"This is not a machine PHI node that we are updating!");
- PHI->addRegOperand(PHINodesToUpdate[i].second);
+ PHI->addRegOperand(PHINodesToUpdate[i].second, false);
PHI->addMachineBasicBlockOperand(BB);
}
return;
@@ -3576,11 +3576,11 @@
assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
"This is not a machine PHI node that we are updating!");
if (PHIBB == JT.Default) {
- PHI->addRegOperand(PHINodesToUpdate[pi].second);
+ PHI->addRegOperand(PHINodesToUpdate[pi].second, false);
PHI->addMachineBasicBlockOperand(RangeBB);
}
if (BB->succ_end() != std::find(BB->succ_begin(),BB->succ_end(), PHIBB))
{
- PHI->addRegOperand(PHINodesToUpdate[pi].second);
+ PHI->addRegOperand(PHINodesToUpdate[pi].second, false);
PHI->addMachineBasicBlockOperand(BB);
}
}
@@ -3610,7 +3610,7 @@
assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
"This is not a machine PHI node that we are updating!");
if (PHIBB == SwitchCases[i].LHSBB || PHIBB == SwitchCases[i].RHSBB) {
- PHI->addRegOperand(PHINodesToUpdate[pi].second);
+ PHI->addRegOperand(PHINodesToUpdate[pi].second, false);
PHI->addMachineBasicBlockOperand(BB);
}
}
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