Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAGList.cpp updated: 1.62 -> 1.63
ScheduleDAGRRList.cpp updated: 1.9 -> 1.10
ScheduleDAGSimple.cpp updated: 1.13 -> 1.14
SelectionDAGISel.cpp updated: 1.262 -> 1.263
---
Log message:
Introducing plugable register allocators and instruction schedulers.
---
Diffs of the changes: (+87 -82)
ScheduleDAGList.cpp | 19 ++++++----
ScheduleDAGRRList.cpp | 18 +++++++--
ScheduleDAGSimple.cpp | 37 ++++++++++++++++---
SelectionDAGISel.cpp | 95 +++++++++++++++-----------------------------------
4 files changed, 87 insertions(+), 82 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp:1.62
llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp:1.63
--- llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp:1.62 Thu Jul 20
12:28:38 2006
+++ llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp Tue Aug 1 09:21:23 2006
@@ -19,6 +19,7 @@
//===----------------------------------------------------------------------===//
#define DEBUG_TYPE "sched"
+#include "llvm/CodeGen/MachinePassRegistry.h"
#include "llvm/CodeGen/ScheduleDAG.h"
#include "llvm/CodeGen/SSARegMap.h"
#include "llvm/Target/MRegisterInfo.h"
@@ -38,6 +39,10 @@
static Statistic<> NumStalls("scheduler", "Number of pipeline stalls");
}
+static RegisterScheduler
+ tdListDAGScheduler("list-td", " Top-down list scheduler",
+ createTDListDAGScheduler);
+
namespace {
//===----------------------------------------------------------------------===//
/// ScheduleDAGList - The actual list scheduler implementation. This supports
@@ -511,12 +516,12 @@
// Public Constructor Functions
//===----------------------------------------------------------------------===//
-/// createTDListDAGScheduler - This creates a top-down list scheduler with the
-/// specified hazard recognizer.
-ScheduleDAG* llvm::createTDListDAGScheduler(SelectionDAG &DAG,
- MachineBasicBlock *BB,
- HazardRecognizer *HR) {
- return new ScheduleDAGList(DAG, BB, DAG.getTarget(),
+/// createTDListDAGScheduler - This creates a top-down list scheduler with a
+/// new hazard recognizer. This scheduler takes ownership of the hazard
+/// recognizer and deletes it when done.
+ScheduleDAG* llvm::createTDListDAGScheduler(SelectionDAG *DAG,
+ MachineBasicBlock *BB) {
+ return new ScheduleDAGList(*DAG, BB, DAG->getTarget(),
new LatencyPriorityQueue(),
- HR);
+ new HazardRecognizer());
}
Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp:1.9
llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp:1.10
--- llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp:1.9 Fri Jul 21
15:57:35 2006
+++ llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Tue Aug 1 09:21:23 2006
@@ -16,6 +16,7 @@
//===----------------------------------------------------------------------===//
#define DEBUG_TYPE "sched"
+#include "llvm/CodeGen/MachinePassRegistry.h"
#include "llvm/CodeGen/ScheduleDAG.h"
#include "llvm/CodeGen/SSARegMap.h"
#include "llvm/Target/MRegisterInfo.h"
@@ -31,6 +32,15 @@
#include "llvm/Support/CommandLine.h"
using namespace llvm;
+static RegisterScheduler
+ burrListDAGScheduler("list-burr",
+ " Bottom-up register reduction list scheduling",
+ createBURRListDAGScheduler);
+static RegisterScheduler
+ tdrListrDAGScheduler("list-tdrr",
+ " Top-down register reduction list scheduling",
+ createTDRRListDAGScheduler);
+
namespace {
//===----------------------------------------------------------------------===//
/// ScheduleDAGRRList - The actual register reduction list scheduler
@@ -876,15 +886,15 @@
// Public Constructor Functions
//===----------------------------------------------------------------------===//
-llvm::ScheduleDAG* llvm::createBURRListDAGScheduler(SelectionDAG &DAG,
+llvm::ScheduleDAG* llvm::createBURRListDAGScheduler(SelectionDAG *DAG,
MachineBasicBlock *BB) {
- return new ScheduleDAGRRList(DAG, BB, DAG.getTarget(), true,
+ return new ScheduleDAGRRList(*DAG, BB, DAG->getTarget(), true,
new
BURegReductionPriorityQueue<bu_ls_rr_sort>());
}
-llvm::ScheduleDAG* llvm::createTDRRListDAGScheduler(SelectionDAG &DAG,
+llvm::ScheduleDAG* llvm::createTDRRListDAGScheduler(SelectionDAG *DAG,
MachineBasicBlock *BB) {
- return new ScheduleDAGRRList(DAG, BB, DAG.getTarget(), false,
+ return new ScheduleDAGRRList(*DAG, BB, DAG->getTarget(), false,
new
TDRegReductionPriorityQueue<td_ls_rr_sort>());
}
Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSimple.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSimple.cpp:1.13
llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSimple.cpp:1.14
--- llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSimple.cpp:1.13 Wed Jun 28
17:17:39 2006
+++ llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSimple.cpp Tue Aug 1 09:21:23 2006
@@ -14,6 +14,7 @@
//===----------------------------------------------------------------------===//
#define DEBUG_TYPE "sched"
+#include "llvm/CodeGen/MachinePassRegistry.h"
#include "llvm/CodeGen/ScheduleDAG.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/Target/TargetData.h"
@@ -25,7 +26,23 @@
#include <iostream>
using namespace llvm;
+
namespace {
+
+static RegisterScheduler
+ bfsDAGScheduler("none", " No scheduling: breadth first sequencing",
+ createBFS_DAGScheduler);
+static RegisterScheduler
+ simpleDAGScheduler("simple",
+ " Simple two pass scheduling: minimize critical path "
+ "and maximize processor utilization",
+ createSimpleDAGScheduler);
+static RegisterScheduler
+ noitinDAGScheduler("simple-noitin",
+ " Simple two pass scheduling: Same as simple "
+ "except using generic latency",
+ createNoItinsDAGScheduler);
+
class NodeInfo;
typedef NodeInfo *NodeInfoPtr;
typedef std::vector<NodeInfoPtr> NIVector;
@@ -1102,14 +1119,22 @@
/// createSimpleDAGScheduler - This creates a simple two pass instruction
-/// scheduler.
-llvm::ScheduleDAG* llvm::createSimpleDAGScheduler(bool NoItins,
- SelectionDAG &DAG,
+/// scheduler using instruction itinerary.
+llvm::ScheduleDAG* llvm::createSimpleDAGScheduler(SelectionDAG *DAG,
MachineBasicBlock *BB) {
- return new ScheduleDAGSimple(false, NoItins, DAG, BB, DAG.getTarget());
+ return new ScheduleDAGSimple(false, false, *DAG, BB, DAG->getTarget());
}
-llvm::ScheduleDAG* llvm::createBFS_DAGScheduler(SelectionDAG &DAG,
+/// createNoItinsDAGScheduler - This creates a simple two pass instruction
+/// scheduler without using instruction itinerary.
+llvm::ScheduleDAG* llvm::createNoItinsDAGScheduler(SelectionDAG *DAG,
+ MachineBasicBlock *BB) {
+ return new ScheduleDAGSimple(false, true, *DAG, BB, DAG->getTarget());
+}
+
+/// createBFS_DAGScheduler - This creates a simple breadth first instruction
+/// scheduler.
+llvm::ScheduleDAG* llvm::createBFS_DAGScheduler(SelectionDAG *DAG,
MachineBasicBlock *BB) {
- return new ScheduleDAGSimple(true, false, DAG, BB, DAG.getTarget());
+ return new ScheduleDAGSimple(true, false, *DAG, BB, DAG->getTarget());
}
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.262
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.263
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.262 Mon Jul 31
20:03:13 2006
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Tue Aug 1 09:21:23 2006
@@ -29,6 +29,7 @@
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineJumpTableInfo.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/CodeGen/MachinePassRegistry.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/SSARegMap.h"
#include "llvm/Target/MRegisterInfo.h"
@@ -60,41 +61,14 @@
static const bool ViewISelDAGs = 0, ViewSchedDAGs = 0;
#endif
-// Scheduling heuristics
-enum SchedHeuristics {
- defaultScheduling, // Let the target specify its preference.
- noScheduling, // No scheduling, emit breadth first sequence.
- simpleScheduling, // Two pass, min. critical path, max. utilization.
- simpleNoItinScheduling, // Same as above exact using generic latency.
- listSchedulingBURR, // Bottom-up reg reduction list scheduling.
- listSchedulingTDRR, // Top-down reg reduction list scheduling.
- listSchedulingTD // Top-down list scheduler.
-};
-
namespace {
- cl::opt<SchedHeuristics>
- ISHeuristic(
- "sched",
- cl::desc("Choose scheduling style"),
- cl::init(defaultScheduling),
- cl::values(
- clEnumValN(defaultScheduling, "default",
- "Target preferred scheduling style"),
- clEnumValN(noScheduling, "none",
- "No scheduling: breadth first sequencing"),
- clEnumValN(simpleScheduling, "simple",
- "Simple two pass scheduling: minimize critical path "
- "and maximize processor utilization"),
- clEnumValN(simpleNoItinScheduling, "simple-noitin",
- "Simple two pass scheduling: Same as simple "
- "except using generic latency"),
- clEnumValN(listSchedulingBURR, "list-burr",
- "Bottom-up register reduction list scheduling"),
- clEnumValN(listSchedulingTDRR, "list-tdrr",
- "Top-down register reduction list scheduling"),
- clEnumValN(listSchedulingTD, "list-td",
- "Top-down list scheduler"),
- clEnumValEnd));
+ cl::opt<const char *, false, RegisterPassParser<RegisterScheduler> >
+ ISHeuristic("sched",
+ cl::init("default"),
+ cl::desc("Instruction schedulers available:"));
+
+ RegisterScheduler
+ defaultListDAGScheduler("default", " Best scheduler for the target", NULL);
} // namespace
namespace {
@@ -3629,50 +3603,41 @@
}
}
+
//===----------------------------------------------------------------------===//
/// ScheduleAndEmitDAG - Pick a safe ordering and emit instructions for each
/// target node in the graph.
void SelectionDAGISel::ScheduleAndEmitDAG(SelectionDAG &DAG) {
if (ViewSchedDAGs) DAG.viewGraph();
- ScheduleDAG *SL = NULL;
- switch (ISHeuristic) {
- default: assert(0 && "Unrecognized scheduling heuristic");
- case defaultScheduling:
- if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency)
- SL = createTDListDAGScheduler(DAG, BB, CreateTargetHazardRecognizer());
- else {
- assert(TLI.getSchedulingPreference() ==
+ static RegisterScheduler::FunctionPassCtor Ctor =
+
RegisterScheduler::getCache();
+
+ if (!Ctor) {
+ if (std::string("default") == std::string(ISHeuristic)) {
+ if (TLI.getSchedulingPreference() ==
TargetLowering::SchedulingForLatency)
+ Ctor = RegisterScheduler::FindCtor("list-td");
+ else {
+ assert(TLI.getSchedulingPreference() ==
TargetLowering::SchedulingForRegPressure && "Unknown sched
type!");
- SL = createBURRListDAGScheduler(DAG, BB);
+ Ctor = RegisterScheduler::FindCtor("list-burr");
+ }
+
+ assert(Ctor && "Default instruction scheduler not present");
+ if (!Ctor) Ctor = RegisterScheduler::FindCtor("none");
+ } else {
+ Ctor = RegisterScheduler::FindCtor(ISHeuristic);
}
- break;
- case noScheduling:
- SL = createBFS_DAGScheduler(DAG, BB);
- break;
- case simpleScheduling:
- SL = createSimpleDAGScheduler(false, DAG, BB);
- break;
- case simpleNoItinScheduling:
- SL = createSimpleDAGScheduler(true, DAG, BB);
- break;
- case listSchedulingBURR:
- SL = createBURRListDAGScheduler(DAG, BB);
- break;
- case listSchedulingTDRR:
- SL = createTDRRListDAGScheduler(DAG, BB);
- break;
- case listSchedulingTD:
- SL = createTDListDAGScheduler(DAG, BB, CreateTargetHazardRecognizer());
- break;
+
+ RegisterScheduler::setCache(Ctor);
}
+
+ assert(Ctor && "No instruction scheduler found");
+ ScheduleDAG *SL = Ctor(&DAG, BB);
BB = SL->Run();
delete SL;
}
-HazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() {
- return new HazardRecognizer();
-}
/// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
/// by tblgen. Others should not call it.
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