Changes in directory llvm/lib/Target/PowerPC:
PPCRegisterInfo.cpp updated: 1.68 -> 1.69
---
Log message:
Gaar! Don't use r11 for CR save/restore, use R0. R11 can be register
allocated, thus live across the save/reload. This fixes
llc-beta /MultiSource/Applications/spiff/spiff
llc-beta /MultiSource/Benchmarks/sim/sim:
llc-beta /MultiSource/Benchmarks/Ptrdist/bc/bc
llc-beta /MultiSource/Benchmarks/McCat/12-IOtest/iotest:
llc-beta /MultiSource/Benchmarks/FreeBench/fourinarow/fourinarow
llc-beta /MultiSource/Benchmarks/Fhourstones-3.1/fhourstones3.1
llc-beta /MultiSource/Benchmarks/mediabench/adpcm/rawdaudio/rawdaudio
llc-beta /MultiSource/Benchmarks/mediabench/adpcm/rawcaudio/rawcaudio
llc-beta /MultiSource/Benchmarks/mediabench/g721/g721encode/encode
llc-beta /MultiSource/Benchmarks/mediabench/jpeg/jpeg-6a/cjpeg
and probably others, with -regalloc=local.
---
Diffs of the changes: (+11 -9)
PPCRegisterInfo.cpp | 20 +++++++++++---------
1 files changed, 11 insertions(+), 9 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.68
llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.69
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.68 Mon Jun 12 16:50:57 2006
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp Mon Jun 12 18:59:16 2006
@@ -102,20 +102,21 @@
BuildMI(MBB, MI, PPC::MFLR, 1, PPC::R11);
addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(PPC::R11),
FrameIdx);
} else if (RC == PPC::CRRCRegisterClass) {
+ // FIXME: We use R0 here, because it isn't available for RA.
// We need to store the CR in the low 4-bits of the saved value. First,
// issue a MFCR to save all of the CRBits.
- BuildMI(MBB, MI, PPC::MFCR, 0, PPC::R11);
+ BuildMI(MBB, MI, PPC::MFCR, 0, PPC::R0);
// If the saved register wasn't CR0, shift the bits left so that they are
in
// CR0's slot.
if (SrcReg != PPC::CR0) {
unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(SrcReg)*4;
- // rlwinm r11, r11, ShiftBits, 0, 31.
- BuildMI(MBB, MI, PPC::RLWINM, 4, PPC::R11)
- .addReg(PPC::R11).addImm(ShiftBits).addImm(0).addImm(31);
+ // rlwinm r0, r0, ShiftBits, 0, 31.
+ BuildMI(MBB, MI, PPC::RLWINM, 4, PPC::R0)
+ .addReg(PPC::R0).addImm(ShiftBits).addImm(0).addImm(31);
}
- addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(PPC::R11),
FrameIdx);
+ addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(PPC::R0), FrameIdx);
} else if (RC == PPC::GPRCRegisterClass) {
addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(SrcReg),FrameIdx);
} else if (RC == PPC::G8RCRegisterClass) {
@@ -148,18 +149,19 @@
addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, PPC::R11), FrameIdx);
BuildMI(MBB, MI, PPC::MTLR, 1).addReg(PPC::R11);
} else if (RC == PPC::CRRCRegisterClass) {
- addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, PPC::R11), FrameIdx);
+ // FIXME: We use R0 here, because it isn't available for RA.
+ addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, PPC::R0), FrameIdx);
// If the reloaded register isn't CR0, shift the bits right so that they
are
// in the right CR's slot.
if (DestReg != PPC::CR0) {
unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(DestReg)*4;
// rlwinm r11, r11, 32-ShiftBits, 0, 31.
- BuildMI(MBB, MI, PPC::RLWINM, 4, PPC::R11)
- .addReg(PPC::R11).addImm(32-ShiftBits).addImm(0).addImm(31);
+ BuildMI(MBB, MI, PPC::RLWINM, 4, PPC::R0)
+ .addReg(PPC::R0).addImm(32-ShiftBits).addImm(0).addImm(31);
}
- BuildMI(MBB, MI, PPC::MTCRF, 1, DestReg).addReg(PPC::R11);
+ BuildMI(MBB, MI, PPC::MTCRF, 1, DestReg).addReg(PPC::R0);
} else if (RC == PPC::GPRCRegisterClass) {
addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, DestReg), FrameIdx);
} else if (RC == PPC::G8RCRegisterClass) {
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