Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.29 -> 1.30
---
Log message:
Added SSE cachebility ops
---
Diffs of the changes: (+30 -0)
X86InstrSSE.td | 30 ++++++++++++++++++++++++++++++
1 files changed, 30 insertions(+)
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.29
llvm/lib/Target/X86/X86InstrSSE.td:1.30
--- llvm/lib/Target/X86/X86InstrSSE.td:1.29 Fri Mar 24 19:33:37 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Sat Mar 25 00:03:26 2006
@@ -891,6 +891,36 @@
// Miscellaneous Instructions
//===----------------------------------------------------------------------===//
+// Prefetching loads
+def PREFETCHT0 : I<0x18, MRM1m, (ops i8mem:$src),
+ "prefetcht0 $src", []>, TB,
+ Requires<[HasSSE1]>;
+def PREFETCHT1 : I<0x18, MRM2m, (ops i8mem:$src),
+ "prefetcht0 $src", []>, TB,
+ Requires<[HasSSE1]>;
+def PREFETCHT2 : I<0x18, MRM3m, (ops i8mem:$src),
+ "prefetcht0 $src", []>, TB,
+ Requires<[HasSSE1]>;
+def PREFETCHTNTA : I<0x18, MRM0m, (ops i8mem:$src),
+ "prefetcht0 $src", []>, TB,
+ Requires<[HasSSE1]>;
+
+// Non-temporal stores
+def MOVNTQ : I<0xE7, MRMDestMem, (ops i64mem:$dst, VR64:$src),
+ "movntq {$src, $dst|$dst, $src}", []>, TB,
+ Requires<[HasSSE1]>;
+def MOVNTPS : I<0x2B, MRMDestMem, (ops i128mem:$dst, VR128:$src),
+ "movntps {$src, $dst|$dst, $src}", []>, TB,
+ Requires<[HasSSE1]>;
+def MASKMOVQ : I<0xF7, MRMDestMem, (ops i64mem:$dst, VR64:$src),
+ "maskmovq {$src, $dst|$dst, $src}", []>, TB,
+ Requires<[HasSSE1]>;
+
+// Store fence
+def SFENCE : I<0xAE, MRM7m, (ops),
+ "sfence", []>, TB, Requires<[HasSSE1]>;
+
+// Load MXCSR register
def LDMXCSR : I<0xAE, MRM2m, (ops i32mem:$src),
"ldmxcsr {$src|$src}", []>, TB, Requires<[HasSSE1]>;
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