Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.326 -> 1.327
SelectionDAG.cpp updated: 1.276 -> 1.277
SelectionDAGISel.cpp updated: 1.197 -> 1.198
---
Log message:
Add a hacky workaround for crashes due to vectors live across blocks.
Note that this code won't work for vectors that aren't legal on the
target. Improvements coming.
---
Diffs of the changes: (+31 -1)
LegalizeDAG.cpp | 3 +++
SelectionDAG.cpp | 3 ++-
SelectionDAGISel.cpp | 26 ++++++++++++++++++++++++++
3 files changed, 31 insertions(+), 1 deletion(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.326
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.327
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.326 Sun Mar 19 19:52:29 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Tue Mar 21 13:20:37 2006
@@ -4262,6 +4262,9 @@
/// type for the result.
SDOperand SelectionDAGLegalize::PackVectorOp(SDOperand Op,
MVT::ValueType NewVT) {
+ // FIXME: THIS IS A TEMPORARY HACK
+ if (Op.getValueType() == NewVT) return Op;
+
assert(Op.getValueType() == MVT::Vector && "Bad PackVectorOp invocation!");
SDNode *Node = Op.Val;
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.276
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.277
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.276 Sun Mar 19
17:56:04 2006
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Tue Mar 21 13:20:37 2006
@@ -1086,7 +1086,8 @@
break;
case ISD::BIT_CONVERT:
// Basic sanity checking.
- assert(MVT::getSizeInBits(VT) == MVT::getSizeInBits(Operand.getValueType())
+ assert((Operand.getValueType() == MVT::Vector || // FIXME: This is a
hack.
+ MVT::getSizeInBits(VT) ==
MVT::getSizeInBits(Operand.getValueType()))
&& "Cannot BIT_CONVERT between two different types!");
if (VT == Operand.getValueType()) return Operand; // noop conversion.
if (OpOpcode == ISD::BIT_CONVERT) // bitconv(bitconv(x)) -> bitconv(x)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.197
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.198
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.197 Sat Mar 18
19:17:20 2006
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Tue Mar 21 13:20:37 2006
@@ -2285,6 +2285,32 @@
SelectionDAG &DAG = SDL.DAG;
if (SrcVT == DestVT) {
return DAG.getCopyToReg(SDL.getRoot(), Reg, Op);
+ } else if (SrcVT == MVT::Vector) {
+ // FIXME: THIS DOES NOT SUPPORT PROMOTED/EXPANDED ELEMENTS!
+
+ // Figure out the right, legal destination reg to copy into.
+ const PackedType *PTy = cast<PackedType>(V->getType());
+ unsigned NumElts = PTy->getNumElements();
+ MVT::ValueType EltTy = TLI.getValueType(PTy->getElementType());
+
+ unsigned NumVectorRegs = 1;
+
+ // Divide the input until we get to a supported size. This will always
+ // end with a scalar if the target doesn't support vectors.
+ while (NumElts > 1 && !TLI.isTypeLegal(getVectorType(EltTy, NumElts))) {
+ NumElts >>= 1;
+ NumVectorRegs <<= 1;
+ }
+
+ MVT::ValueType VT;
+ if (NumElts == 1)
+ VT = EltTy;
+ else
+ VT = getVectorType(EltTy, NumElts);
+
+ // FIXME: THIS ASSUMES THAT THE INPUT VECTOR WILL BE LEGAL!
+ Op = DAG.getNode(ISD::BIT_CONVERT, VT, Op);
+ return DAG.getCopyToReg(SDL.getRoot(), Reg, Op);
} else if (SrcVT < DestVT) {
// The src value is promoted to the register.
if (MVT::isFloatingPoint(SrcVT))
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