Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.92 -> 1.93 --- Log message: Turn any_extend nodes into zero_extend nodes when it allows us to remove an and instruction. This allows us to compile stuff like this: bool %X(int %X) { %Y = add int %X, 14 %Z = setne int %Y, 12345 ret bool %Z } to this: _X: cmpl $12331, 4(%esp) setne %al movzbl %al, %eax ret instead of this: _X: cmpl $12331, 4(%esp) setne %al movzbl %al, %eax andl $1, %eax ret This occurs quite a bit with the X86 backend. For example, 25 times in lambda, 30 times in 177.mesa, 14 times in galgel, 70 times in fma3d, 25 times in vpr, several hundred times in gcc, ~45 times in crafty, ~60 times in parser, ~140 times in eon, 110 times in perlbmk, 55 on gap, 16 times on bzip2, 14 times on twolf, and 1-2 times in many other SPEC2K programs. --- Diffs of the changes: (+13 -0) DAGCombiner.cpp | 13 +++++++++++++ 1 files changed, 13 insertions(+) Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.92 llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.93 --- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.92 Thu Feb 2 00:36:13 2006 +++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Thu Feb 2 01:17:31 2006 @@ -889,6 +889,19 @@ if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) if ((ORI->getValue() & N1C->getValue()) == N1C->getValue()) return N1; + // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits. + if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { + unsigned InBits = MVT::getSizeInBits(N0.getOperand(0).getValueType()); + if (TLI.MaskedValueIsZero(N0.getOperand(0), + ~N1C->getValue() & ((1ULL << InBits)-1))) { + // We actually want to replace all uses of the any_extend with the + // zero_extend, to avoid duplicating things. This will later cause this + // AND to be folded. + CombineTo(N0.Val, DAG.getNode(ISD::ZERO_EXTEND, N0.getValueType(), + N0.getOperand(0))); + return SDOperand(); + } + } // fold (and (setcc x), (setcc y)) -> (setcc (and x, y)) if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); _______________________________________________ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits