Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.99 -> 1.100 --- Log message: Compile this: xori r6, r2, 1 rlwinm r6, r6, 0, 31, 31 cmpwi cr0, r6, 0 bne cr0, LBB1_3 ; endif to this: rlwinm r6, r2, 0, 31, 31 cmpwi cr0, r6, 0 beq cr0, LBB1_3 ; endif --- Diffs of the changes: (+26 -0) DAGCombiner.cpp | 26 ++++++++++++++++++++++++++ 1 files changed, 26 insertions(+) Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.99 llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.100 --- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.99 Sun Feb 5 02:23:00 2006 +++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Tue Feb 7 20:13:15 2006 @@ -2544,6 +2544,32 @@ DAG.getConstant(C1 & (~0ULL>>(64-ExtSrcTyBits)), ExtDstTy), Cond); + } else if ((N1C->getValue() == 0 || N1C->getValue() == 1) && + (Cond == ISD::SETEQ || Cond == ISD::SETNE) && + (N0.getOpcode() == ISD::XOR || + (N0.getOpcode() == ISD::AND && + N0.getOperand(0).getOpcode() == ISD::XOR && + N0.getOperand(1) == N0.getOperand(0).getOperand(1))) && + isa<ConstantSDNode>(N0.getOperand(1)) && + cast<ConstantSDNode>(N0.getOperand(1))->getValue() == 1) { + // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We can + // only do this if the top bits are known zero. + if (TLI.MaskedValueIsZero(N1, + MVT::getIntVTBitMask(N0.getValueType())-1)) { + // Okay, get the un-inverted input value. + SDOperand Val; + if (N0.getOpcode() == ISD::XOR) + Val = N0.getOperand(0); + else { + assert(N0.getOpcode() == ISD::AND && + N0.getOperand(0).getOpcode() == ISD::XOR); + // ((X^1)&1)^1 -> X & 1 + Val = DAG.getNode(ISD::AND, N0.getValueType(), + N0.getOperand(0).getOperand(0), N0.getOperand(1)); + } + return DAG.getSetCC(VT, Val, N1, + Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ); + } } uint64_t MinVal, MaxVal; _______________________________________________ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits