Changes in directory llvm/lib/Target/SparcV8:
SparcV8ISelDAGToDAG.cpp updated: 1.62 -> 1.63
---
Log message:
Implement isMaskedValueZeroForTargetNode for the various v8 selectcc nodes,
allowing redundant and's to be eliminated by the dag combiner.
---
Diffs of the changes: (+26 -0)
SparcV8ISelDAGToDAG.cpp | 26 ++++++++++++++++++++++++++
1 files changed, 26 insertions(+)
Index: llvm/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp
diff -u llvm/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp:1.62
llvm/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp:1.63
--- llvm/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp:1.62 Fri Jan 27
17:30:03 2006
+++ llvm/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp Sun Jan 29 21:51:45 2006
@@ -57,6 +57,14 @@
public:
SparcV8TargetLowering(TargetMachine &TM);
virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
+
+ /// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to
+ /// be zero. Op is expected to be a target specific node. Used by DAG
+ /// combiner.
+ virtual bool isMaskedValueZeroForTargetNode(const SDOperand &Op,
+ uint64_t Mask,
+ MVIZFnPtr MVIZ) const;
+
virtual std::vector<SDOperand>
LowerArguments(Function &F, SelectionDAG &DAG);
virtual std::pair<SDOperand, SDOperand>
@@ -191,6 +199,24 @@
}
}
+/// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to
+/// be zero. Op is expected to be a target specific node. Used by DAG
+/// combiner.
+bool SparcV8TargetLowering::
+isMaskedValueZeroForTargetNode(const SDOperand &Op, uint64_t Mask,
+ MVIZFnPtr MVIZ) const {
+ switch (Op.getOpcode()) {
+ default: return false;
+ case V8ISD::SELECT_ICC:
+ case V8ISD::SELECT_FCC:
+ assert(MVT::isInteger(Op.getValueType()) && "Not an integer select!");
+ // These operations are masked zero if both the left and the right are
zero.
+ return MVIZ(Op.getOperand(0), Mask, *this) &&
+ MVIZ(Op.getOperand(1), Mask, *this);
+ }
+}
+
+
/// LowerArguments - V8 uses a very simple ABI, where all values are passed in
/// either one or two GPRs, including FP values. TODO: we should pass FP
values
/// in FP registers for fastcc functions.
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