Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.58 -> 1.59 --- Log message: Fix a source of undefined behavior when dealing with 64-bit types. This may fix PR652: http://llvm.cs.uiuc.edu/PR652 . Thanks to Andrew for tracking down the problem. --- Diffs of the changes: (+1 -1) DAGCombiner.cpp | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.58 llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.59 --- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.58 Sun Oct 30 01:41:49 2005 +++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Tue Nov 1 19:47:04 2005 @@ -384,7 +384,7 @@ return (Mask & ((1ULL << SrcBits)-1)) == 0; // Returning only the zext bits. case ISD::ZERO_EXTEND: SrcBits = MVT::getSizeInBits(Op.getOperand(0).getValueType()); - return MaskedValueIsZero(Op.getOperand(0),Mask & ((1ULL << SrcBits)-1),TLI); + return MaskedValueIsZero(Op.getOperand(0),Mask & (~0ULL >> (64-SrcBits)),TLI); case ISD::AssertZext: SrcBits = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(1))->getVT()); return (Mask & ((1ULL << SrcBits)-1)) == 0; // Returning only the zext bits. _______________________________________________ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
