Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.62 -> 1.63
---
Log message:
Teach the dag combiner to turn a truncate/sign_extend pair into a sextinreg
when the types match up. This allows the X86 backend to compile:
sbyte %toggle_value(sbyte* %tmp.1) {
%tmp.2 = load sbyte* %tmp.1
ret sbyte %tmp.2
}
to this:
_toggle_value:
mov %EAX, DWORD PTR [%ESP + 4]
movsx %EAX, BYTE PTR [%EAX]
ret
instead of this:
_toggle_value:
mov %EAX, DWORD PTR [%ESP + 4]
movsx %EAX, BYTE PTR [%EAX]
movsx %EAX, %AL
ret
noticed in Shootout/objinst.
-Chris
---
Diffs of the changes: (+4 -0)
DAGCombiner.cpp | 4 ++++
1 files changed, 4 insertions(+)
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.62
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.63
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.62 Fri Nov 11 18:59:01 2005
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Wed Dec 7 01:11:03 2005
@@ -1546,6 +1546,10 @@
// fold (sext (sextload x)) -> (sextload x)
if (N0.getOpcode() == ISD::SEXTLOAD && VT == N0.getValueType())
return N0;
+ // fold (sext (truncate x)) -> (sextinreg x) iff x size == sext size.
+ if (N0.getOpcode() == ISD::TRUNCATE && N0.getOperand(0).getValueType() == VT)
+ return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0),
+ DAG.getValueType(N0.getValueType()));
// fold (sext (load x)) -> (sextload x)
if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse()) {
SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0),
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