https://github.com/tomershafir updated
https://github.com/llvm/llvm-project/pull/148428
>From 9efe85048c2f68b724949172898fb4880ad8b4a4 Mon Sep 17 00:00:00 2001
From: tomershafir <tomer.shaf...@gmail.com>
Date: Tue, 15 Jul 2025 12:39:26 +0300
Subject: [PATCH 1/3] git log
Created using spr 1.3.6
---
llvm/lib/Target/AArch64/AArch64Subtarget.cpp | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64Subtarget.cpp
b/llvm/lib/Target/AArch64/AArch64Subtarget.cpp
index d87f91d0fcc91..b9a17df297e14 100644
--- a/llvm/lib/Target/AArch64/AArch64Subtarget.cpp
+++ b/llvm/lib/Target/AArch64/AArch64Subtarget.cpp
@@ -678,10 +678,10 @@ bool AArch64Subtarget::isRegInClass(const MachineInstr
*MI, const Register &Reg,
const TargetRegisterClass *TRC) const {
if (Reg.isPhysical()) {
return TRC->contains(Reg);
- } else {
- const MachineRegisterInfo &MRI = MI->getMF()->getRegInfo();
- return TRC->hasSubClassEq(MRI.getRegClass(Reg));
}
+
+ const MachineRegisterInfo &MRI = MI->getMF()->getRegInfo();
+ return TRC->hasSubClassEq(MRI.getRegClass(Reg));
}
/// NOTE: must maintain consistency with `AArch64InstrInfo::copyPhysReg`.
>From 087cb19a09c3da5022a87e9d99d5c54d4e9b1db8 Mon Sep 17 00:00:00 2001
From: tomershafir <tomer.shaf...@gmail.com>
Date: Tue, 15 Jul 2025 12:44:49 +0300
Subject: [PATCH 2/3] remove redundant else block
Created using spr 1.3.6
---
llvm/lib/Target/AArch64/AArch64Subtarget.cpp | 1 -
1 file changed, 1 deletion(-)
diff --git a/llvm/lib/Target/AArch64/AArch64Subtarget.cpp
b/llvm/lib/Target/AArch64/AArch64Subtarget.cpp
index b9a17df297e14..86b17ed787432 100644
--- a/llvm/lib/Target/AArch64/AArch64Subtarget.cpp
+++ b/llvm/lib/Target/AArch64/AArch64Subtarget.cpp
@@ -679,7 +679,6 @@ bool AArch64Subtarget::isRegInClass(const MachineInstr *MI,
const Register &Reg,
if (Reg.isPhysical()) {
return TRC->contains(Reg);
}
-
const MachineRegisterInfo &MRI = MI->getMF()->getRegInfo();
return TRC->hasSubClassEq(MRI.getRegClass(Reg));
}
>From f286dd5d1f0abaa275408bb2db33f798ffeb828a Mon Sep 17 00:00:00 2001
From: tomershafir <tomer.shaf...@gmail.com>
Date: Tue, 15 Jul 2025 19:06:21 +0300
Subject: [PATCH 3/3] change MI type from pointer to reference
Created using spr 1.3.6
---
llvm/include/llvm/CodeGen/TargetSubtargetInfo.h | 4 ++--
llvm/lib/Target/AArch64/AArch64Subtarget.cpp | 8 ++++----
llvm/lib/Target/AArch64/AArch64Subtarget.h | 6 +++---
3 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/TargetSubtargetInfo.h
b/llvm/include/llvm/CodeGen/TargetSubtargetInfo.h
index c5a7ed19d54dd..ed298f92ef757 100644
--- a/llvm/include/llvm/CodeGen/TargetSubtargetInfo.h
+++ b/llvm/include/llvm/CodeGen/TargetSubtargetInfo.h
@@ -200,7 +200,7 @@ class LLVM_ABI TargetSubtargetInfo : public MCSubtargetInfo
{
///
/// NOTE: Subtargets must maintain consistency between the logic here and
/// on lowering.
- virtual bool canLowerToZeroCycleRegMove(const MachineInstr *CopyMI,
+ virtual bool canLowerToZeroCycleRegMove(const MachineInstr &CopyMI,
const Register &DestReg,
const Register &SrcReg) const {
return false;
@@ -221,7 +221,7 @@ class LLVM_ABI TargetSubtargetInfo : public MCSubtargetInfo
{
///
/// NOTE: Subtargets must maintain consistency between the logic here and
/// on lowering.
- virtual bool canLowerToZeroCycleRegZeroing(const MachineInstr *CopyMI,
+ virtual bool canLowerToZeroCycleRegZeroing(const MachineInstr &CopyMI,
const Register &DestReg,
const Register &SrcReg) const {
return false;
diff --git a/llvm/lib/Target/AArch64/AArch64Subtarget.cpp
b/llvm/lib/Target/AArch64/AArch64Subtarget.cpp
index 86b17ed787432..e562f360d7bd5 100644
--- a/llvm/lib/Target/AArch64/AArch64Subtarget.cpp
+++ b/llvm/lib/Target/AArch64/AArch64Subtarget.cpp
@@ -674,18 +674,18 @@ bool AArch64Subtarget::enableMachinePipeliner() const {
return getSchedModel().hasInstrSchedModel();
}
-bool AArch64Subtarget::isRegInClass(const MachineInstr *MI, const Register
&Reg,
+bool AArch64Subtarget::isRegInClass(const MachineInstr &MI, const Register
&Reg,
const TargetRegisterClass *TRC) const {
if (Reg.isPhysical()) {
return TRC->contains(Reg);
}
- const MachineRegisterInfo &MRI = MI->getMF()->getRegInfo();
+ const MachineRegisterInfo &MRI = MI.getMF()->getRegInfo();
return TRC->hasSubClassEq(MRI.getRegClass(Reg));
}
/// NOTE: must maintain consistency with `AArch64InstrInfo::copyPhysReg`.
bool AArch64Subtarget::canLowerToZeroCycleRegMove(
- const MachineInstr *CopyMI, const Register &DestReg,
+ const MachineInstr &CopyMI, const Register &DestReg,
const Register &SrcReg) const {
if (isRegInClass(CopyMI, DestReg, &AArch64::GPR32allRegClass) &&
isRegInClass(CopyMI, SrcReg, &AArch64::GPR32allRegClass) &&
@@ -737,7 +737,7 @@ bool AArch64Subtarget::canLowerToZeroCycleRegMove(
/// NOTE: must maintain consistency with `AArch64InstrInfo::copyPhysReg`.
bool AArch64Subtarget::canLowerToZeroCycleRegZeroing(
- const MachineInstr *CopyMI, const Register &DestReg,
+ const MachineInstr &CopyMI, const Register &DestReg,
const Register &SrcReg) const {
if (isRegInClass(CopyMI, DestReg, &AArch64::GPR32allRegClass) &&
isRegInClass(CopyMI, SrcReg, &AArch64::GPR32allRegClass) &&
diff --git a/llvm/lib/Target/AArch64/AArch64Subtarget.h
b/llvm/lib/Target/AArch64/AArch64Subtarget.h
index 638febd1cd3d1..3ef0a6727c90e 100644
--- a/llvm/lib/Target/AArch64/AArch64Subtarget.h
+++ b/llvm/lib/Target/AArch64/AArch64Subtarget.h
@@ -123,7 +123,7 @@ class AArch64Subtarget final : public
AArch64GenSubtargetInfo {
/// Returns true if Reg is virtual and is assigned to,
/// or is physcial and is a member of, the TRC register class.
/// Otherwise, returns false.
- bool isRegInClass(const MachineInstr *MI, const Register &Reg,
+ bool isRegInClass(const MachineInstr &MI, const Register &Reg,
const TargetRegisterClass *TRC) const;
public:
@@ -169,10 +169,10 @@ class AArch64Subtarget final : public
AArch64GenSubtargetInfo {
bool enableMachinePipeliner() const override;
bool useDFAforSMS() const override { return false; }
- bool canLowerToZeroCycleRegMove(const MachineInstr *CopyMI,
+ bool canLowerToZeroCycleRegMove(const MachineInstr &CopyMI,
const Register &DestReg,
const Register &SrcReg) const override;
- bool canLowerToZeroCycleRegZeroing(const MachineInstr *CopyMI,
+ bool canLowerToZeroCycleRegZeroing(const MachineInstr &CopyMI,
const Register &DestReg,
const Register &SrcReg) const override;
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