https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/119540
>From d46079681ec362badafa66b61c1a857fb042f67d Mon Sep 17 00:00:00 2001
From: Akshat Oke <akshat....@amd.com>
Date: Wed, 11 Dec 2024 08:51:55 +0000
Subject: [PATCH 1/4] [CodeGen][NewPM] Port RegAllocGreedy to NPM
---
llvm/include/llvm/CodeGen/MachineFunction.h | 1 +
llvm/include/llvm/CodeGen/Passes.h | 2 +-
llvm/include/llvm/InitializePasses.h | 2 +-
.../llvm/Passes/MachinePassRegistry.def | 9 +
llvm/lib/CodeGen/CodeGen.cpp | 2 +-
llvm/lib/CodeGen/RegAllocGreedy.cpp | 185 ++++++++++++++----
llvm/lib/CodeGen/RegAllocGreedy.h | 57 +++---
llvm/lib/Passes/PassBuilder.cpp | 1 +
8 files changed, 196 insertions(+), 63 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/MachineFunction.h
b/llvm/include/llvm/CodeGen/MachineFunction.h
index d696add8a1af53..662272e5e09618 100644
--- a/llvm/include/llvm/CodeGen/MachineFunction.h
+++ b/llvm/include/llvm/CodeGen/MachineFunction.h
@@ -901,6 +901,7 @@ class LLVM_ABI MachineFunction {
/// Run the current MachineFunction through the machine code verifier, useful
/// for debugger use.
+ /// TODO: Add the param LiveStks
/// \returns true if no problems were found.
bool verify(LiveIntervals *LiveInts, SlotIndexes *Indexes,
const char *Banner = nullptr, raw_ostream *OS = nullptr,
diff --git a/llvm/include/llvm/CodeGen/Passes.h
b/llvm/include/llvm/CodeGen/Passes.h
index d1fac4a304cffe..1096c34b307f9b 100644
--- a/llvm/include/llvm/CodeGen/Passes.h
+++ b/llvm/include/llvm/CodeGen/Passes.h
@@ -167,7 +167,7 @@ namespace llvm {
extern char &LiveRangeShrinkID;
/// Greedy register allocator.
- extern char &RAGreedyID;
+ extern char &RAGreedyLegacyID;
/// Basic register allocator.
extern char &RABasicID;
diff --git a/llvm/include/llvm/InitializePasses.h
b/llvm/include/llvm/InitializePasses.h
index e74b85c0de886f..afe0aa6113dd21 100644
--- a/llvm/include/llvm/InitializePasses.h
+++ b/llvm/include/llvm/InitializePasses.h
@@ -250,7 +250,7 @@ void
initializeProfileSummaryInfoWrapperPassPass(PassRegistry &);
void initializePromoteLegacyPassPass(PassRegistry &);
void initializeRABasicPass(PassRegistry &);
void initializePseudoProbeInserterPass(PassRegistry &);
-void initializeRAGreedyPass(PassRegistry &);
+void initializeRAGreedyLegacyPass(PassRegistry &);
void initializeReachingDefAnalysisPass(PassRegistry &);
void initializeReassociateLegacyPassPass(PassRegistry &);
void initializeRegAllocEvictionAdvisorAnalysisLegacyPass(PassRegistry &);
diff --git a/llvm/include/llvm/Passes/MachinePassRegistry.def
b/llvm/include/llvm/Passes/MachinePassRegistry.def
index 2d36c569cf2827..0e526e2d3781d9 100644
--- a/llvm/include/llvm/Passes/MachinePassRegistry.def
+++ b/llvm/include/llvm/Passes/MachinePassRegistry.def
@@ -187,6 +187,15 @@ MACHINE_FUNCTION_PASS_WITH_PARAMS(
return parseRegAllocFastPassOptions(*PB, Params);
},
"filter=reg-filter;no-clear-vregs")
+
+MACHINE_FUNCTION_PASS_WITH_PARAMS(
+ "regallocgreedy", "RAGreedy",
+ [](RegAllocFilterFunc F) { return RAGreedyPass(F); },
+ [PB = this](StringRef Params) {
+ // TODO: parseRegAllocFilter(*PB, Params);
+ return Expected<RegAllocFilterFunc>(nullptr);
+ }, ""
+)
#undef MACHINE_FUNCTION_PASS_WITH_PARAMS
// After a pass is converted to new pass manager, its entry should be moved
from
diff --git a/llvm/lib/CodeGen/CodeGen.cpp b/llvm/lib/CodeGen/CodeGen.cpp
index 8efe540770913a..6acff9cd21134b 100644
--- a/llvm/lib/CodeGen/CodeGen.cpp
+++ b/llvm/lib/CodeGen/CodeGen.cpp
@@ -111,7 +111,7 @@ void llvm::initializeCodeGen(PassRegistry &Registry) {
initializePreISelIntrinsicLoweringLegacyPassPass(Registry);
initializeProcessImplicitDefsPass(Registry);
initializeRABasicPass(Registry);
- initializeRAGreedyPass(Registry);
+ initializeRAGreedyLegacyPass(Registry);
initializeRegAllocFastPass(Registry);
initializeRegUsageInfoCollectorLegacyPass(Registry);
initializeRegUsageInfoPropagationLegacyPass(Registry);
diff --git a/llvm/lib/CodeGen/RegAllocGreedy.cpp
b/llvm/lib/CodeGen/RegAllocGreedy.cpp
index 38f8cb1330a93e..efc0493d25037f 100644
--- a/llvm/lib/CodeGen/RegAllocGreedy.cpp
+++ b/llvm/lib/CodeGen/RegAllocGreedy.cpp
@@ -43,8 +43,10 @@
#include "llvm/CodeGen/MachineLoopInfo.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineOptimizationRemarkEmitter.h"
+#include "llvm/CodeGen/MachinePassManager.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/RegAllocEvictionAdvisor.h"
+#include "llvm/CodeGen/RegAllocGreedyPass.h"
#include "llvm/CodeGen/RegAllocPriorityAdvisor.h"
#include "llvm/CodeGen/RegAllocRegistry.h"
#include "llvm/CodeGen/RegisterClassInfo.h"
@@ -55,6 +57,7 @@
#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/CodeGen/VirtRegMap.h"
+#include "llvm/IR/Analysis.h"
#include "llvm/IR/DebugInfoMetadata.h"
#include "llvm/IR/Function.h"
#include "llvm/IR/LLVMContext.h"
@@ -146,11 +149,134 @@ static cl::opt<unsigned> SplitThresholdForRegWithHint(
static RegisterRegAlloc greedyRegAlloc("greedy", "greedy register allocator",
createGreedyRegisterAllocator);
-char RAGreedy::ID = 0;
-char &llvm::RAGreedyID = RAGreedy::ID;
+namespace {
+class RAGreedyLegacy : public MachineFunctionPass {
+ RegAllocFilterFunc F;
-INITIALIZE_PASS_BEGIN(RAGreedy, "greedy",
- "Greedy Register Allocator", false, false)
+public:
+ RAGreedyLegacy(const RegAllocFilterFunc F = nullptr);
+
+ static char ID;
+ /// Return the pass name.
+ StringRef getPassName() const override { return "Greedy Register Allocator";
}
+
+ /// RAGreedy analysis usage.
+ void getAnalysisUsage(AnalysisUsage &AU) const override;
+ /// Perform register allocation.
+ bool runOnMachineFunction(MachineFunction &mf) override;
+
+ MachineFunctionProperties getRequiredProperties() const override {
+ return MachineFunctionProperties().set(
+ MachineFunctionProperties::Property::NoPHIs);
+ }
+
+ MachineFunctionProperties getClearedProperties() const override {
+ return MachineFunctionProperties().set(
+ MachineFunctionProperties::Property::IsSSA);
+ }
+};
+
+} // end anonymous namespace
+
+RAGreedyLegacy::RAGreedyLegacy(const RegAllocFilterFunc F)
+ : MachineFunctionPass(ID), F(F) {
+ initializeRAGreedyLegacyPass(*PassRegistry::getPassRegistry());
+}
+
+RAGreedy::RAGreedy(const RegAllocFilterFunc F) : RegAllocBase(F) {}
+
+void RAGreedy::setAnalyses(RequiredAnalyses &Analyses) {
+ VRM = Analyses.VRM;
+ LIS = Analyses.LIS;
+ Matrix = Analyses.LRM;
+ Indexes = Analyses.Indexes;
+ MBFI = Analyses.MBFI;
+ DomTree = Analyses.DomTree;
+ Loops = Analyses.Loops;
+ ORE = Analyses.ORE;
+ Bundles = Analyses.Bundles;
+ SpillPlacer = Analyses.SpillPlacer;
+ DebugVars = Analyses.DebugVars;
+ LSS = Analyses.LSS;
+ EvictProvider = Analyses.EvictProvider;
+ PriorityProvider = Analyses.PriorityProvider;
+}
+
+PreservedAnalyses RAGreedyPass::run(MachineFunction &MF,
+ MachineFunctionAnalysisManager &MFAM) {
+ MFPropsModifier _(*this, MF);
+
+ RAGreedy Impl(Filter);
+ RAGreedy::RequiredAnalyses Analyses;
+
+ Analyses.VRM = &MFAM.getResult<VirtRegMapAnalysis>(MF);
+ Analyses.LIS = &MFAM.getResult<LiveIntervalsAnalysis>(MF);
+ Analyses.LRM = &MFAM.getResult<LiveRegMatrixAnalysis>(MF);
+ Analyses.LSS = &MFAM.getResult<LiveStacksAnalysis>(MF);
+ Analyses.Indexes = &MFAM.getResult<SlotIndexesAnalysis>(MF);
+ Analyses.MBFI = &MFAM.getResult<MachineBlockFrequencyAnalysis>(MF);
+ Analyses.DomTree = &MFAM.getResult<MachineDominatorTreeAnalysis>(MF);
+ Analyses.ORE = &MFAM.getResult<MachineOptimizationRemarkEmitterAnalysis>(MF);
+ Analyses.Loops = &MFAM.getResult<MachineLoopAnalysis>(MF);
+ Analyses.Bundles = &MFAM.getResult<EdgeBundlesAnalysis>(MF);
+ Analyses.SpillPlacer = &MFAM.getResult<SpillPlacementAnalysis>(MF);
+ Analyses.DebugVars = &MFAM.getResult<LiveDebugVariablesAnalysis>(MF);
+ Analyses.EvictProvider =
+ MFAM.getResult<RegAllocEvictionAdvisorAnalysis>(MF).Provider;
+ Analyses.PriorityProvider =
+ MFAM.getResult<RegAllocPriorityAdvisorAnalysis>(MF).Provider;
+
+ Impl.setAnalyses(Analyses);
+ bool Changed = Impl.run(MF);
+ if (!Changed)
+ return PreservedAnalyses::all();
+ auto PA = getMachineFunctionPassPreservedAnalyses();
+ PA.preserveSet<CFGAnalyses>();
+ PA.preserve<MachineBlockFrequencyAnalysis>();
+ PA.preserve<LiveIntervalsAnalysis>();
+ PA.preserve<SlotIndexesAnalysis>();
+ PA.preserve<LiveDebugVariablesAnalysis>();
+ PA.preserve<LiveStacksAnalysis>();
+ PA.preserve<MachineDominatorTreeAnalysis>();
+ PA.preserve<MachineLoopAnalysis>();
+ PA.preserve<VirtRegMapAnalysis>();
+ PA.preserve<LiveRegMatrixAnalysis>();
+ return PA;
+}
+
+bool RAGreedyLegacy::runOnMachineFunction(MachineFunction &MF) {
+ RAGreedy Impl(F);
+
+ RAGreedy::RequiredAnalyses Analyses;
+ Analyses.VRM = &getAnalysis<VirtRegMapWrapperLegacy>().getVRM();
+ Analyses.LIS = &getAnalysis<LiveIntervalsWrapperPass>().getLIS();
+ Analyses.LSS = &getAnalysis<LiveStacksWrapperLegacy>().getLS();
+ Analyses.LRM = &getAnalysis<LiveRegMatrixWrapperLegacy>().getLRM();
+ Analyses.Indexes = &getAnalysis<SlotIndexesWrapperPass>().getSI();
+ Analyses.MBFI =
+ &getAnalysis<MachineBlockFrequencyInfoWrapperPass>().getMBFI();
+ Analyses.DomTree =
+ &getAnalysis<MachineDominatorTreeWrapperPass>().getDomTree();
+ Analyses.ORE = &getAnalysis<MachineOptimizationRemarkEmitterPass>().getORE();
+ Analyses.Loops = &getAnalysis<MachineLoopInfoWrapperPass>().getLI();
+ Analyses.Bundles = &getAnalysis<EdgeBundlesWrapperLegacy>().getEdgeBundles();
+ Analyses.SpillPlacer =
+ &getAnalysis<SpillPlacementWrapperLegacy>().getResult();
+ Analyses.DebugVars =
&getAnalysis<LiveDebugVariablesWrapperLegacy>().getLDV();
+ Analyses.EvictProvider =
+ getAnalysis<RegAllocEvictionAdvisorAnalysisLegacy>().getProvider().get();
+ Analyses.PriorityProvider =
+ getAnalysis<RegAllocPriorityAdvisorAnalysisLegacy>().getProvider().get();
+
+ Impl.setAnalyses(Analyses);
+ return Impl.run(MF);
+}
+
+char RAGreedyLegacy::ID = 0;
+char &llvm::RAGreedyLegacyID = RAGreedyLegacy::ID;
+
+INITIALIZE_PASS_BEGIN(RAGreedyLegacy, "greedy", "Greedy Register Allocator",
+ false, false)
INITIALIZE_PASS_DEPENDENCY(LiveDebugVariablesWrapperLegacy)
INITIALIZE_PASS_DEPENDENCY(SlotIndexesWrapperPass)
INITIALIZE_PASS_DEPENDENCY(LiveIntervalsWrapperPass)
@@ -166,8 +292,8 @@ INITIALIZE_PASS_DEPENDENCY(SpillPlacementWrapperLegacy)
INITIALIZE_PASS_DEPENDENCY(MachineOptimizationRemarkEmitterPass)
INITIALIZE_PASS_DEPENDENCY(RegAllocEvictionAdvisorAnalysisLegacy)
INITIALIZE_PASS_DEPENDENCY(RegAllocPriorityAdvisorAnalysisLegacy)
-INITIALIZE_PASS_END(RAGreedy, "greedy",
- "Greedy Register Allocator", false, false)
+INITIALIZE_PASS_END(RAGreedyLegacy, "greedy", "Greedy Register Allocator",
+ false, false)
#ifndef NDEBUG
const char *const RAGreedy::StageName[] = {
@@ -186,17 +312,14 @@ const char *const RAGreedy::StageName[] = {
const float Hysteresis = (2007 / 2048.0f); // 0.97998046875
FunctionPass* llvm::createGreedyRegisterAllocator() {
- return new RAGreedy();
+ return new RAGreedyLegacy();
}
FunctionPass *llvm::createGreedyRegisterAllocator(RegAllocFilterFunc Ftor) {
- return new RAGreedy(Ftor);
+ return new RAGreedyLegacy(Ftor);
}
-RAGreedy::RAGreedy(RegAllocFilterFunc F)
- : MachineFunctionPass(ID), RegAllocBase(F) {}
-
-void RAGreedy::getAnalysisUsage(AnalysisUsage &AU) const {
+void RAGreedyLegacy::getAnalysisUsage(AnalysisUsage &AU) const {
AU.setPreservesCFG();
AU.addRequired<MachineBlockFrequencyInfoWrapperPass>();
AU.addPreserved<MachineBlockFrequencyInfoWrapperPass>();
@@ -1057,7 +1180,8 @@ void RAGreedy::splitAroundRegion(LiveRangeEdit &LREdit,
}
if (VerifyEnabled)
- MF->verify(this, "After splitting live range around region", &errs());
+ MF->verify(LIS, Indexes, "After splitting live range around region",
+ &errs());
}
MCRegister RAGreedy::tryRegionSplit(const LiveInterval &VirtReg,
@@ -1326,7 +1450,8 @@ unsigned RAGreedy::tryBlockSplit(const LiveInterval
&VirtReg,
}
if (VerifyEnabled)
- MF->verify(this, "After splitting live range around basic blocks",
&errs());
+ MF->verify(LIS, Indexes, "After splitting live range around basic blocks",
+ &errs());
return 0;
}
@@ -2524,7 +2649,7 @@ MCRegister RAGreedy::selectOrSplitImpl(const LiveInterval
&VirtReg,
DebugVars->splitRegister(r, LRE.regs(), *LIS);
if (VerifyEnabled)
- MF->verify(this, "After spilling", &errs());
+ MF->verify(LIS, Indexes, "After spilling", &errs());
}
// The live virtual register requesting allocation was spilled, so tell
@@ -2720,7 +2845,7 @@ bool RAGreedy::hasVirtRegAlloc() {
return false;
}
-bool RAGreedy::runOnMachineFunction(MachineFunction &mf) {
+bool RAGreedy::run(MachineFunction &mf) {
LLVM_DEBUG(dbgs() << "********** GREEDY REGISTER ALLOCATION **********\n"
<< "********** Function: " << mf.getName() << '\n');
@@ -2728,29 +2853,18 @@ bool RAGreedy::runOnMachineFunction(MachineFunction
&mf) {
TII = MF->getSubtarget().getInstrInfo();
if (VerifyEnabled)
- MF->verify(this, "Before greedy register allocator", &errs());
+ MF->verify(LIS, Indexes, "Before greedy register allocator", &errs());
- RegAllocBase::init(getAnalysis<VirtRegMapWrapperLegacy>().getVRM(),
- getAnalysis<LiveIntervalsWrapperPass>().getLIS(),
- getAnalysis<LiveRegMatrixWrapperLegacy>().getLRM());
+ RegAllocBase::init(*this->VRM, *this->LIS, *this->Matrix);
// Early return if there is no virtual register to be allocated to a
// physical register.
if (!hasVirtRegAlloc())
return false;
- Indexes = &getAnalysis<SlotIndexesWrapperPass>().getSI();
// Renumber to get accurate and consistent results from
// SlotIndexes::getApproxInstrDistance.
Indexes->packIndexes();
- MBFI = &getAnalysis<MachineBlockFrequencyInfoWrapperPass>().getMBFI();
- DomTree = &getAnalysis<MachineDominatorTreeWrapperPass>().getDomTree();
- ORE = &getAnalysis<MachineOptimizationRemarkEmitterPass>().getORE();
- Loops = &getAnalysis<MachineLoopInfoWrapperPass>().getLI();
- Bundles = &getAnalysis<EdgeBundlesWrapperLegacy>().getEdgeBundles();
- SpillPlacer = &getAnalysis<SpillPlacementWrapperLegacy>().getResult();
- DebugVars = &getAnalysis<LiveDebugVariablesWrapperLegacy>().getLDV();
- auto &LSS = getAnalysis<LiveStacksWrapperLegacy>().getLS();
initializeCSRCost();
@@ -2766,17 +2880,12 @@ bool RAGreedy::runOnMachineFunction(MachineFunction
&mf) {
ExtraInfo.emplace();
- auto &EvictAdvisorProvider =
- getAnalysis<RegAllocEvictionAdvisorAnalysisLegacy>().getProvider();
- EvictAdvisor = EvictAdvisorProvider->getAdvisor(*MF, *this, MBFI, Loops);
-
- PriorityAdvisor = getAnalysis<RegAllocPriorityAdvisorAnalysisLegacy>()
- .getProvider()
- ->getAdvisor(*MF, *this, Indexes);
+ EvictAdvisor = EvictProvider->getAdvisor(*MF, *this, MBFI, Loops);
+ PriorityAdvisor = PriorityProvider->getAdvisor(*MF, *this, Indexes);
VRAI = std::make_unique<VirtRegAuxInfo>(*MF, *LIS, *VRM, *Loops, *MBFI);
SpillerInstance.reset(
- createInlineSpiller({*LIS, LSS, *DomTree, *MBFI}, *MF, *VRM, *VRAI));
+ createInlineSpiller({*LIS, *LSS, *DomTree, *MBFI}, *MF, *VRM, *VRAI));
VRAI->calculateSpillWeightsAndHints();
@@ -2793,7 +2902,7 @@ bool RAGreedy::runOnMachineFunction(MachineFunction &mf) {
tryHintsRecoloring();
if (VerifyEnabled)
- MF->verify(this, "Before post optimization", &errs());
+ MF->verify(LIS, Indexes, "Before post optimization", &errs());
postOptimization();
reportStats();
diff --git a/llvm/lib/CodeGen/RegAllocGreedy.h
b/llvm/lib/CodeGen/RegAllocGreedy.h
index 89ceefd37795bc..278ffd0ed906b5 100644
--- a/llvm/lib/CodeGen/RegAllocGreedy.h
+++ b/llvm/lib/CodeGen/RegAllocGreedy.h
@@ -25,13 +25,15 @@
#include "llvm/CodeGen/LiveDebugVariables.h"
#include "llvm/CodeGen/LiveInterval.h"
#include "llvm/CodeGen/LiveRangeEdit.h"
+#include "llvm/CodeGen/LiveStacks.h"
#include "llvm/CodeGen/MachineFunction.h"
-#include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/RegAllocEvictionAdvisor.h"
#include "llvm/CodeGen/RegAllocPriorityAdvisor.h"
#include "llvm/CodeGen/RegisterClassInfo.h"
#include "llvm/CodeGen/SpillPlacement.h"
#include "llvm/CodeGen/Spiller.h"
#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/IR/PassManager.h"
#include <algorithm>
#include <cstdint>
#include <memory>
@@ -56,11 +58,30 @@ class SlotIndexes;
class TargetInstrInfo;
class VirtRegMap;
-class LLVM_LIBRARY_VISIBILITY RAGreedy : public MachineFunctionPass,
- public RegAllocBase,
+class LLVM_LIBRARY_VISIBILITY RAGreedy : public RegAllocBase,
private LiveRangeEdit::Delegate {
- // Interface to eviction advisers
public:
+ struct RequiredAnalyses {
+ VirtRegMap *VRM = nullptr;
+ LiveIntervals *LIS = nullptr;
+ LiveRegMatrix *LRM = nullptr;
+ SlotIndexes *Indexes = nullptr;
+ MachineBlockFrequencyInfo *MBFI = nullptr;
+ MachineDominatorTree *DomTree = nullptr;
+ MachineLoopInfo *Loops = nullptr;
+ MachineOptimizationRemarkEmitter *ORE = nullptr;
+ EdgeBundles *Bundles = nullptr;
+ SpillPlacement *SpillPlacer = nullptr;
+ LiveDebugVariables *DebugVars = nullptr;
+
+ // Used by InlineSpiller
+ LiveStacks *LSS;
+ // Proxies for eviction and priority advisors
+ RegAllocEvictionAdvisorProvider *EvictProvider;
+ RegAllocPriorityAdvisorProvider *PriorityProvider;
+ };
+
+ // Interface to eviction advisers
/// Track allocation stage and eviction loop prevention during allocation.
class ExtraRegInfo final {
// RegInfo - Keep additional information about each live range.
@@ -178,6 +199,10 @@ class LLVM_LIBRARY_VISIBILITY RAGreedy : public
MachineFunctionPass,
EdgeBundles *Bundles = nullptr;
SpillPlacement *SpillPlacer = nullptr;
LiveDebugVariables *DebugVars = nullptr;
+ LiveStacks *LSS = nullptr; // Used by InlineSpiller
+ // Proxy for the advisors
+ RegAllocEvictionAdvisorProvider *EvictProvider = nullptr;
+ RegAllocPriorityAdvisorProvider *PriorityProvider = nullptr;
// state
std::unique_ptr<Spiller> SpillerInstance;
@@ -282,13 +307,11 @@ class LLVM_LIBRARY_VISIBILITY RAGreedy : public
MachineFunctionPass,
public:
RAGreedy(const RegAllocFilterFunc F = nullptr);
+ // Evict and priority advisors use this object, so we can construct those
+ // first and pass them here.
+ // Not required once legacy PM is removed.
+ void setAnalyses(RequiredAnalyses &Analyses);
- /// Return the pass name.
- StringRef getPassName() const override { return "Greedy Register Allocator";
}
-
- /// RAGreedy analysis usage.
- void getAnalysisUsage(AnalysisUsage &AU) const override;
- void releaseMemory() override;
Spiller &spiller() override { return *SpillerInstance; }
void enqueueImpl(const LiveInterval *LI) override;
const LiveInterval *dequeue() override;
@@ -297,19 +320,9 @@ class LLVM_LIBRARY_VISIBILITY RAGreedy : public
MachineFunctionPass,
void aboutToRemoveInterval(const LiveInterval &) override;
/// Perform register allocation.
- bool runOnMachineFunction(MachineFunction &mf) override;
-
- MachineFunctionProperties getRequiredProperties() const override {
- return MachineFunctionProperties().set(
- MachineFunctionProperties::Property::NoPHIs);
- }
-
- MachineFunctionProperties getClearedProperties() const override {
- return MachineFunctionProperties().set(
- MachineFunctionProperties::Property::IsSSA);
- }
+ bool run(MachineFunction &mf);
- static char ID;
+ void releaseMemory();
private:
MCRegister selectOrSplitImpl(const LiveInterval &,
diff --git a/llvm/lib/Passes/PassBuilder.cpp b/llvm/lib/Passes/PassBuilder.cpp
index a71493f609dc6a..3a9db2dbd59226 100644
--- a/llvm/lib/Passes/PassBuilder.cpp
+++ b/llvm/lib/Passes/PassBuilder.cpp
@@ -125,6 +125,7 @@
#include "llvm/CodeGen/PreISelIntrinsicLowering.h"
#include "llvm/CodeGen/RegAllocEvictionAdvisor.h"
#include "llvm/CodeGen/RegAllocFast.h"
+#include "llvm/CodeGen/RegAllocGreedyPass.h"
#include "llvm/CodeGen/RegAllocPriorityAdvisor.h"
#include "llvm/CodeGen/RegUsageInfoCollector.h"
#include "llvm/CodeGen/RegUsageInfoPropagate.h"
>From 0bc6507648a5f5c1f05f8ee6d08152d7a08f37ca Mon Sep 17 00:00:00 2001
From: Akshat Oke <akshat....@amd.com>
Date: Fri, 13 Dec 2024 10:59:04 +0000
Subject: [PATCH 2/4] Move pass to a new header, add options
---
.../include/llvm/CodeGen/RegAllocGreedyPass.h | 43 +++++++++++++++++++
llvm/include/llvm/Passes/CodeGenPassBuilder.h | 1 +
.../llvm/Passes/MachinePassRegistry.def | 11 +++--
llvm/lib/CodeGen/RegAllocGreedy.cpp | 7 ++-
4 files changed, 55 insertions(+), 7 deletions(-)
create mode 100644 llvm/include/llvm/CodeGen/RegAllocGreedyPass.h
diff --git a/llvm/include/llvm/CodeGen/RegAllocGreedyPass.h
b/llvm/include/llvm/CodeGen/RegAllocGreedyPass.h
new file mode 100644
index 00000000000000..f325224c5384cb
--- /dev/null
+++ b/llvm/include/llvm/CodeGen/RegAllocGreedyPass.h
@@ -0,0 +1,43 @@
+//==- RegAllocGreedyPass.h --- greedy register allocator pass
------*-C++-*-==//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+#include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/RegAllocCommon.h"
+#include "llvm/CodeGen/RegAllocFast.h"
+#include "llvm/IR/PassManager.h"
+
+using namespace llvm;
+
+class RAGreedyPass : public PassInfoMixin<RAGreedyPass> {
+
+public:
+ struct Options {
+ RegAllocFilterFunc Filter;
+ StringRef FilterName;
+ Options(RegAllocFilterFunc F = nullptr, StringRef FN = "all")
+ : Filter(F), FilterName(FN) {};
+ };
+
+ RAGreedyPass(Options Opts = Options()) : Opts(Opts) {}
+ PreservedAnalyses run(MachineFunction &F, MachineFunctionAnalysisManager
&AM);
+
+ MachineFunctionProperties getRequiredProperties() const {
+ return MachineFunctionProperties().set(
+ MachineFunctionProperties::Property::NoPHIs);
+ }
+
+ MachineFunctionProperties getClearedProperties() const {
+ return MachineFunctionProperties().set(
+ MachineFunctionProperties::Property::IsSSA);
+ }
+
+ void printPipeline(raw_ostream &OS, function_ref<StringRef(StringRef)>
MapClassName2PassName) const;
+ static bool isRequired() { return true; }
+
+private:
+ Options Opts;
+};
diff --git a/llvm/include/llvm/Passes/CodeGenPassBuilder.h
b/llvm/include/llvm/Passes/CodeGenPassBuilder.h
index 50f548b3a92e04..aca9b3b888acc3 100644
--- a/llvm/include/llvm/Passes/CodeGenPassBuilder.h
+++ b/llvm/include/llvm/Passes/CodeGenPassBuilder.h
@@ -56,6 +56,7 @@
#include "llvm/CodeGen/PreISelIntrinsicLowering.h"
#include "llvm/CodeGen/RegAllocEvictionAdvisor.h"
#include "llvm/CodeGen/RegAllocFast.h"
+#include "llvm/CodeGen/RegAllocGreedyPass.h"
#include "llvm/CodeGen/RegUsageInfoCollector.h"
#include "llvm/CodeGen/RegUsageInfoPropagate.h"
#include "llvm/CodeGen/RegisterUsageInfo.h"
diff --git a/llvm/include/llvm/Passes/MachinePassRegistry.def
b/llvm/include/llvm/Passes/MachinePassRegistry.def
index 0e526e2d3781d9..5facdfa825e4cb 100644
--- a/llvm/include/llvm/Passes/MachinePassRegistry.def
+++ b/llvm/include/llvm/Passes/MachinePassRegistry.def
@@ -189,12 +189,12 @@ MACHINE_FUNCTION_PASS_WITH_PARAMS(
"filter=reg-filter;no-clear-vregs")
MACHINE_FUNCTION_PASS_WITH_PARAMS(
- "regallocgreedy", "RAGreedy",
- [](RegAllocFilterFunc F) { return RAGreedyPass(F); },
+ "regallocgreedy", "RAGreedyPass",
+ [](RAGreedyPass::Options Opts) { return RAGreedyPass(Opts); },
[PB = this](StringRef Params) {
- // TODO: parseRegAllocFilter(*PB, Params);
- return Expected<RegAllocFilterFunc>(nullptr);
- }, ""
+ // TODO: parseRegAllocGreedyFilterFunc(*PB, Params);
+ return Expected<RAGreedyPass::Options>(RAGreedyPass::Options{});
+ }, "reg-filter"
)
#undef MACHINE_FUNCTION_PASS_WITH_PARAMS
@@ -266,7 +266,6 @@ DUMMY_MACHINE_FUNCTION_PASS("processimpdefs",
ProcessImplicitDefsPass)
DUMMY_MACHINE_FUNCTION_PASS("prologepilog", PrologEpilogInserterPass)
DUMMY_MACHINE_FUNCTION_PASS("prologepilog-code", PrologEpilogCodeInserterPass)
DUMMY_MACHINE_FUNCTION_PASS("ra-basic", RABasicPass)
-DUMMY_MACHINE_FUNCTION_PASS("ra-greedy", RAGreedyPass)
DUMMY_MACHINE_FUNCTION_PASS("ra-pbqp", RAPBQPPass)
DUMMY_MACHINE_FUNCTION_PASS("regalloc", RegAllocPass)
DUMMY_MACHINE_FUNCTION_PASS("regallocscoringpass", RegAllocScoringPass)
diff --git a/llvm/lib/CodeGen/RegAllocGreedy.cpp
b/llvm/lib/CodeGen/RegAllocGreedy.cpp
index efc0493d25037f..820d7a6aab060d 100644
--- a/llvm/lib/CodeGen/RegAllocGreedy.cpp
+++ b/llvm/lib/CodeGen/RegAllocGreedy.cpp
@@ -202,11 +202,16 @@ void RAGreedy::setAnalyses(RequiredAnalyses &Analyses) {
PriorityProvider = Analyses.PriorityProvider;
}
+void RAGreedyPass::printPipeline(raw_ostream &OS,
function_ref<StringRef(StringRef)> MapClassName2PassName) const {
+ StringRef FilterName = Opts.FilterName.empty() ? "all" : Opts.FilterName;
+ OS << "regallocgreedy<" << FilterName << ">";
+}
+
PreservedAnalyses RAGreedyPass::run(MachineFunction &MF,
MachineFunctionAnalysisManager &MFAM) {
MFPropsModifier _(*this, MF);
- RAGreedy Impl(Filter);
+ RAGreedy Impl(Opts.Filter);
RAGreedy::RequiredAnalyses Analyses;
Analyses.VRM = &MFAM.getResult<VirtRegMapAnalysis>(MF);
>From cc636806a684c06b397e98f1883e8a24ddd00207 Mon Sep 17 00:00:00 2001
From: Akshat Oke <akshat....@amd.com>
Date: Mon, 16 Dec 2024 09:34:30 +0000
Subject: [PATCH 3/4] Move VRM after LiveIntervals
---
llvm/lib/CodeGen/RegAllocGreedy.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/CodeGen/RegAllocGreedy.cpp
b/llvm/lib/CodeGen/RegAllocGreedy.cpp
index 820d7a6aab060d..2b5e5c5b168d20 100644
--- a/llvm/lib/CodeGen/RegAllocGreedy.cpp
+++ b/llvm/lib/CodeGen/RegAllocGreedy.cpp
@@ -214,7 +214,6 @@ PreservedAnalyses RAGreedyPass::run(MachineFunction &MF,
RAGreedy Impl(Opts.Filter);
RAGreedy::RequiredAnalyses Analyses;
- Analyses.VRM = &MFAM.getResult<VirtRegMapAnalysis>(MF);
Analyses.LIS = &MFAM.getResult<LiveIntervalsAnalysis>(MF);
Analyses.LRM = &MFAM.getResult<LiveRegMatrixAnalysis>(MF);
Analyses.LSS = &MFAM.getResult<LiveStacksAnalysis>(MF);
@@ -230,6 +229,7 @@ PreservedAnalyses RAGreedyPass::run(MachineFunction &MF,
MFAM.getResult<RegAllocEvictionAdvisorAnalysis>(MF).Provider;
Analyses.PriorityProvider =
MFAM.getResult<RegAllocPriorityAdvisorAnalysis>(MF).Provider;
+ Analyses.VRM = &MFAM.getResult<VirtRegMapAnalysis>(MF);
Impl.setAnalyses(Analyses);
bool Changed = Impl.run(MF);
>From 1b48c6b9f0f2765d9ea54341641846d5879577ad Mon Sep 17 00:00:00 2001
From: Akshat Oke <akshat....@amd.com>
Date: Wed, 1 Jan 2025 08:51:35 +0000
Subject: [PATCH 4/4] AS: Rename to greedy, CFG obviation, comment fix
---
llvm/include/llvm/CodeGen/MachineFunction.h | 2 +-
llvm/include/llvm/Passes/MachinePassRegistry.def | 2 +-
llvm/lib/CodeGen/RegAllocGreedy.cpp | 2 --
3 files changed, 2 insertions(+), 4 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/MachineFunction.h
b/llvm/include/llvm/CodeGen/MachineFunction.h
index 662272e5e09618..41ff503d5329eb 100644
--- a/llvm/include/llvm/CodeGen/MachineFunction.h
+++ b/llvm/include/llvm/CodeGen/MachineFunction.h
@@ -901,7 +901,7 @@ class LLVM_ABI MachineFunction {
/// Run the current MachineFunction through the machine code verifier, useful
/// for debugger use.
- /// TODO: Add the param LiveStks
+ /// TODO: Add the param for LiveStacks analysis.
/// \returns true if no problems were found.
bool verify(LiveIntervals *LiveInts, SlotIndexes *Indexes,
const char *Banner = nullptr, raw_ostream *OS = nullptr,
diff --git a/llvm/include/llvm/Passes/MachinePassRegistry.def
b/llvm/include/llvm/Passes/MachinePassRegistry.def
index 5facdfa825e4cb..fa7f769f31fdde 100644
--- a/llvm/include/llvm/Passes/MachinePassRegistry.def
+++ b/llvm/include/llvm/Passes/MachinePassRegistry.def
@@ -189,7 +189,7 @@ MACHINE_FUNCTION_PASS_WITH_PARAMS(
"filter=reg-filter;no-clear-vregs")
MACHINE_FUNCTION_PASS_WITH_PARAMS(
- "regallocgreedy", "RAGreedyPass",
+ "greedy", "RAGreedyPass",
[](RAGreedyPass::Options Opts) { return RAGreedyPass(Opts); },
[PB = this](StringRef Params) {
// TODO: parseRegAllocGreedyFilterFunc(*PB, Params);
diff --git a/llvm/lib/CodeGen/RegAllocGreedy.cpp
b/llvm/lib/CodeGen/RegAllocGreedy.cpp
index 2b5e5c5b168d20..e0969af048baca 100644
--- a/llvm/lib/CodeGen/RegAllocGreedy.cpp
+++ b/llvm/lib/CodeGen/RegAllocGreedy.cpp
@@ -242,8 +242,6 @@ PreservedAnalyses RAGreedyPass::run(MachineFunction &MF,
PA.preserve<SlotIndexesAnalysis>();
PA.preserve<LiveDebugVariablesAnalysis>();
PA.preserve<LiveStacksAnalysis>();
- PA.preserve<MachineDominatorTreeAnalysis>();
- PA.preserve<MachineLoopAnalysis>();
PA.preserve<VirtRegMapAnalysis>();
PA.preserve<LiveRegMatrixAnalysis>();
return PA;
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