Author: Hsiangkai Wang Date: 2021-01-22T11:33:42+08:00 New Revision: 5d354220d44f11c70f36d5a357ec2a2208a6ab92
URL: https://github.com/llvm/llvm-project/commit/5d354220d44f11c70f36d5a357ec2a2208a6ab92 DIFF: https://github.com/llvm/llvm-project/commit/5d354220d44f11c70f36d5a357ec2a2208a6ab92.diff LOG: [RISCV] Correct DWARF number for vector registers. The DWARF numbers of vector registers are already defined in riscv-elf-psabi. The DWARF number for vector is start from 96. Correct the DWARF numbers of vector registers. Differential Revision: https://reviews.llvm.org/D94749 Added: Modified: llvm/lib/Target/RISCV/RISCVRegisterInfo.td Removed: ################################################################################ diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td index 3b79a10f111b..e1a11fd9389f 100644 --- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td +++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td @@ -411,7 +411,7 @@ class VRegList<list<dag> LIn, int start, int nf, int lmul> { // Vector registers let RegAltNameIndices = [ABIRegAltName] in { foreach Index = 0-31 in { - def V#Index : RISCVReg<Index, "v"#Index, ["v"#Index]>, DwarfRegNum<[!add(Index, 64)]>; + def V#Index : RISCVReg<Index, "v"#Index, ["v"#Index]>, DwarfRegNum<[!add(Index, 96)]>; } foreach Index = [0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
