Author: Craig Topper Date: 2021-01-21T19:29:02-08:00 New Revision: f8f1b20e6b30624d2c0d18dc6a2d61643650d0c4
URL: https://github.com/llvm/llvm-project/commit/f8f1b20e6b30624d2c0d18dc6a2d61643650d0c4 DIFF: https://github.com/llvm/llvm-project/commit/f8f1b20e6b30624d2c0d18dc6a2d61643650d0c4.diff LOG: [RISCV] Don't create LMUL=8 pseudo instructions for ternary widening arithmetic instructions These instructions produce 2*SEW result so the input can't have an LMUL=8 or the result would need a non-existant LMUL=16. So only create pseudos for LMUL up to 4. Differential Revision: https://reviews.llvm.org/D95189 Added: Modified: llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td Removed: ################################################################################ diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td index d1a823be25b6..ab0b2ae00ab1 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td @@ -1581,13 +1581,13 @@ multiclass VPseudoTernaryV_VX_AAXA<bit IsFloat, string Constraint = ""> { multiclass VPseudoTernaryW_VV { defvar constraint = "@earlyclobber $rd"; - foreach m = MxList.m in + foreach m = MxList.m[0-5] in defm _VV : VPseudoTernary<m.wvrclass, m.vrclass, m.vrclass, m, constraint>; } multiclass VPseudoTernaryW_VX<bit IsFloat> { defvar constraint = "@earlyclobber $rd"; - foreach m = MxList.m in + foreach m = MxList.m[0-5] in defm !if(IsFloat, "_VF", "_VX") : VPseudoTernary<m.wvrclass, !if(IsFloat, FPR32, GPR), m.vrclass, m, constraint>; } _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
