Author: Craig Topper Date: 2021-01-09T20:22:07-08:00 New Revision: 6fc7a92eeeb5c47754b875bf6cf1b84687ebe693
URL: https://github.com/llvm/llvm-project/commit/6fc7a92eeeb5c47754b875bf6cf1b84687ebe693 DIFF: https://github.com/llvm/llvm-project/commit/6fc7a92eeeb5c47754b875bf6cf1b84687ebe693.diff LOG: [RISCV] Change ConstraintMask in RISCVII enum to be shifted left. NFC This makes the mask align with the position of the bits in TSFlags which is a little more logical. I might be adding more fields to TSFlags and some might be single bits where just ANDing with mask to test the bit would make sense. While there rename TargetFlags in validateInstruction to reflect that it's just the constraint bits. Added: Modified: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h Removed: ################################################################################ diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp index 975945c9a5e5..257d2f05ee3c 100644 --- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp +++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp @@ -2314,27 +2314,27 @@ std::unique_ptr<RISCVOperand> RISCVAsmParser::defaultMaskRegOp() const { bool RISCVAsmParser::validateInstruction(MCInst &Inst, OperandVector &Operands) { const MCInstrDesc &MCID = MII.get(Inst.getOpcode()); - unsigned TargetFlags = - (MCID.TSFlags >> RISCVII::ConstraintOffset) & RISCVII::ConstraintMask; - if (TargetFlags == RISCVII::NoConstraint) + unsigned Constraints = + (MCID.TSFlags & RISCVII::ConstraintMask) >> RISCVII::ConstraintShift; + if (Constraints == RISCVII::NoConstraint) return false; unsigned DestReg = Inst.getOperand(0).getReg(); // Operands[1] will be the first operand, DestReg. SMLoc Loc = Operands[1]->getStartLoc(); - if (TargetFlags & RISCVII::VS2Constraint) { + if (Constraints & RISCVII::VS2Constraint) { unsigned CheckReg = Inst.getOperand(1).getReg(); if (DestReg == CheckReg) return Error(Loc, "The destination vector register group cannot overlap" " the source vector register group."); } - if ((TargetFlags & RISCVII::VS1Constraint) && (Inst.getOperand(2).isReg())) { + if ((Constraints & RISCVII::VS1Constraint) && (Inst.getOperand(2).isReg())) { unsigned CheckReg = Inst.getOperand(2).getReg(); if (DestReg == CheckReg) return Error(Loc, "The destination vector register group cannot overlap" " the source vector register group."); } - if ((TargetFlags & RISCVII::VMConstraint) && (DestReg == RISCV::V0)) { + if ((Constraints & RISCVII::VMConstraint) && (DestReg == RISCV::V0)) { // vadc, vsbc are special cases. These instructions have no mask register. // The destination register could not be V0. unsigned Opcode = Inst.getOpcode(); diff --git a/llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h b/llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h index 99d8c8e7375f..a6162ef5f852 100644 --- a/llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h +++ b/llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h @@ -47,8 +47,8 @@ enum { InstFormatMask = 31, - ConstraintOffset = 5, - ConstraintMask = 0b111 + ConstraintShift = 5, + ConstraintMask = 0b111 << ConstraintShift, }; // Match with the definitions in RISCVInstrFormatsV.td _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
