Author: pjaaskel
Date: Wed Mar 1 09:44:10 2017
New Revision: 296633
URL: http://llvm.org/viewvc/llvm-project?rev=296633&view=rev
Log:
Added pocl and TCE to releasenotes. Both of them now work with LLVM 4.0
Modified:
llvm/branches/release_40/docs/ReleaseNotes.rst
Modified: llvm/branches/release_40/docs/ReleaseNotes.rst
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_40/docs/ReleaseNotes.rst?rev=296633&r1=296632&r2=296633&view=diff
==============================================================================
--- llvm/branches/release_40/docs/ReleaseNotes.rst (original)
+++ llvm/branches/release_40/docs/ReleaseNotes.rst Wed Mar 1 09:44:10 2017
@@ -308,6 +308,34 @@ x86/x86_64 systems like Linux, OS X, Fre
and PowerPC (32/64 bit). Ports to other architectures like AArch64 and MIPS64
are underway.
+Portable Computing Language (pocl)
+----------------------------------
+
+In addition to producing an easily portable open source OpenCL
+implementation, another major goal of `pocl <http://pocl.sourceforge.net/>`_
+is improving performance portability of OpenCL programs with
+compiler optimizations, reducing the need for target-dependent manual
+optimizations. An important part of pocl is a set of LLVM passes used to
+statically parallelize multiple work-items with the kernel compiler, even in
+the presence of work-group barriers. This enables static parallelization of
+the fine-grained static concurrency in the work groups in multiple ways.
+
+TTA-based Co-design Environment (TCE)
+-------------------------------------
+
+`TCE <http://tce.cs.tut.fi/>`_ is a toolset for designing customized
+processors based on the Transport Triggered Architecture (TTA).
+The toolset provides a complete co-design flow from C/C++
+programs down to synthesizable VHDL/Verilog and parallel program binaries.
+Processor customization points include register files, function units,
+supported operations, and the interconnection network.
+
+TCE uses Clang and LLVM for C/C++/OpenCL C language support, target independent
+optimizations and also for parts of code generation. It generates new
+LLVM-based code generators "on the fly" for the designed TTA processors and
+loads them in to the compiler backend as runtime libraries to avoid
+per-target recompilation of larger parts of the compiler chain.
+
Additional Information
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