Author: dsanders Date: Sat May 28 11:11:08 2016 New Revision: 271126 URL: http://llvm.org/viewvc/llvm-project?rev=271126&view=rev Log: Merging r262230: ------------------------------------------------------------------------ r262230 | vkalintiris | 2016-02-29 15:58:12 +0000 (Mon, 29 Feb 2016) | 7 lines
[mips] Do not use SLL for ANY_EXTEND nodes as the high bits are undefined. Reviewers: dsanders Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D15420 ------------------------------------------------------------------------ Modified: llvm/branches/release_38/lib/Target/Mips/Mips64InstrInfo.td llvm/branches/release_38/test/CodeGen/Mips/cconv/return-struct.ll llvm/branches/release_38/test/CodeGen/Mips/fcopysign-f32-f64.ll Modified: llvm/branches/release_38/lib/Target/Mips/Mips64InstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/lib/Target/Mips/Mips64InstrInfo.td?rev=271126&r1=271125&r2=271126&view=diff ============================================================================== --- llvm/branches/release_38/lib/Target/Mips/Mips64InstrInfo.td (original) +++ llvm/branches/release_38/lib/Target/Mips/Mips64InstrInfo.td Sat May 28 11:11:08 2016 @@ -518,7 +518,8 @@ def : MipsPat<(rotr GPR64:$rt, (i32 (tru (DROTRV GPR64:$rt, (EXTRACT_SUBREG GPR64:$rs, sub_32))>; // 32-to-64-bit extension -def : MipsPat<(i64 (anyext GPR32:$src)), (SLL64_32 GPR32:$src)>; +def : MipsPat<(i64 (anyext GPR32:$src)), + (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$src, sub_32)>; def : MipsPat<(i64 (zext GPR32:$src)), (DSRL (DSLL64_32 GPR32:$src), 32)>; def : MipsPat<(i64 (sext GPR32:$src)), (SLL64_32 GPR32:$src)>; Modified: llvm/branches/release_38/test/CodeGen/Mips/cconv/return-struct.ll URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/test/CodeGen/Mips/cconv/return-struct.ll?rev=271126&r1=271125&r2=271126&view=diff ============================================================================== --- llvm/branches/release_38/test/CodeGen/Mips/cconv/return-struct.ll (original) +++ llvm/branches/release_38/test/CodeGen/Mips/cconv/return-struct.ll Sat May 28 11:11:08 2016 @@ -158,9 +158,6 @@ entry: ; sret pointer is already in $4 ; N32-DAG: lui [[PTR_HI:\$[0-9]+]], %hi(struct_128xi16) ; N32-DAG: addiu [[PTR:\$[0-9]+]], [[PTR_HI]], %lo(struct_128xi16) -; FIXME: This signext isn't necessary. Like integers, pointers are -; but unlike integers, pointers cannot have the signext attribute. -; N32-DAG: sll $5, [[PTR]], 0 ; N32: jal memcpy ; sret pointer is already in $4 Modified: llvm/branches/release_38/test/CodeGen/Mips/fcopysign-f32-f64.ll URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/test/CodeGen/Mips/fcopysign-f32-f64.ll?rev=271126&r1=271125&r2=271126&view=diff ============================================================================== --- llvm/branches/release_38/test/CodeGen/Mips/fcopysign-f32-f64.ll (original) +++ llvm/branches/release_38/test/CodeGen/Mips/fcopysign-f32-f64.ll Sat May 28 11:11:08 2016 @@ -1,6 +1,9 @@ -; RUN: llc < %s -march=mips64el -mcpu=mips4 -target-abi=n64 | FileCheck %s -check-prefix=64 -; RUN: llc < %s -march=mips64el -mcpu=mips64 -target-abi=n64 | FileCheck %s -check-prefix=64 -; RUN: llc < %s -march=mips64el -mcpu=mips64r2 -target-abi=n64 | FileCheck %s -check-prefix=64R2 +; RUN: llc < %s -march=mips64el -mcpu=mips4 -target-abi=n64 | \ +; RUN: FileCheck %s -check-prefix=ALL -check-prefix=64 +; RUN: llc < %s -march=mips64el -mcpu=mips64 -target-abi=n64 | \ +; RUN: FileCheck %s -check-prefix=ALL -check-prefix=64 +; RUN: llc < %s -march=mips64el -mcpu=mips64r2 -target-abi=n64 | \ +; RUN: FileCheck %s -check-prefix=ALL -check-prefix=64R2 declare double @copysign(double, double) nounwind readnone @@ -8,7 +11,8 @@ declare float @copysignf(float, float) n define float @func2(float %d, double %f) nounwind readnone { entry: -; 64: func2 +; ALL-LABEL: func2: + ; 64-DAG: lui $[[T0:[0-9]+]], 32767 ; 64-DAG: ori $[[MSK0:[0-9]+]], $[[T0]], 65535 ; 64-DAG: and $[[AND0:[0-9]+]], ${{[0-9]+}}, $[[MSK0]] @@ -30,17 +34,18 @@ entry: define double @func3(double %d, float %f) nounwind readnone { entry: +; ALL-LABEL: func3: -; 64: func3 -; 64-DAG: daddiu $[[T0:[0-9]+]], $zero, 1 -; 64-DAG: dsll $[[T1:[0-9]+]], $[[T0]], 63 -; 64-DAG: daddiu $[[MSK0:[0-9]+]], $[[T1]], -1 -; 64-DAG: and $[[AND0:[0-9]+]], ${{[0-9]+}}, $[[MSK0]] -; 64-DAG: srl $[[SRL:[0-9]+]], ${{[0-9]+}}, 31 -; 64-DAG: sll $[[SLL:[0-9]+]], $[[SRL]], 0 -; 64-DAG: dsll $[[DSLL:[0-9]+]], $[[SLL]], 63 -; 64: or $[[OR:[0-9]+]], $[[AND0]], $[[DSLL]] -; 64: dmtc1 $[[OR]], $f0 +; 64-DAG: mfc1 $[[MFC:[0-9]+]], $f13 +; 64-DAG: srl $[[SRL:[0-9]+]], $[[MFC:[0-9]+]], 31 +; 64: dsll $[[DSLL:[0-9]+]], $[[SRL]], 63 +; 64-DAG: daddiu $[[R1:[0-9]+]], $zero, 1 +; 64-DAG: dsll $[[R2:[0-9]+]], $[[R1]], 63 +; 64-DAG: daddiu $[[R3:[0-9]+]], $[[R2]], -1 +; 64-DAG: dmfc1 $[[R0:[0-9]+]], ${{.*}} +; 64: and $[[AND0:[0-9]+]], $[[R0]], $[[R3]] +; 64: or $[[OR:[0-9]+]], $[[AND0]], $[[DSLL]] +; 64: dmtc1 $[[OR]], $f0 ; 64R2: ext ${{[0-9]+}}, ${{[0-9]+}}, 31, 1 ; 64R2: dins $[[INS:[0-9]+]], ${{[0-9]+}}, 63, 1 @@ -51,4 +56,3 @@ entry: %call = tail call double @copysign(double %add, double %conv) nounwind readnone ret double %call } - _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
