Author: tstellar
Date: Mon Nov 16 11:23:34 2015
New Revision: 253236
URL: http://llvm.org/viewvc/llvm-project?rev=253236&view=rev
Log:
Merging r248858:
------------------------------------------------------------------------
r248858 | marek.olsak | 2015-09-29 19:37:32 -0400 (Tue, 29 Sep 2015) | 9 lines
AMDGPU/SI: Don't set DATA_FORMAT if ADD_TID_ENABLE is set
to prevent setting a huge stride, because DATA_FORMAT has a different
meaning if ADD_TID_ENABLE is set.
This is a candidate for stable llvm 3.7.
Tested-and-Reviewed-by: Christian König <christian.koe...@amd.com>
------------------------------------------------------------------------
Modified:
llvm/branches/release_37/lib/Target/AMDGPU/SIISelLowering.cpp
llvm/branches/release_37/lib/Target/AMDGPU/SIInstrInfo.cpp
llvm/branches/release_37/lib/Target/AMDGPU/SIInstrInfo.h
llvm/branches/release_37/lib/Target/AMDGPU/SIPrepareScratchRegs.cpp
Modified: llvm/branches/release_37/lib/Target/AMDGPU/SIISelLowering.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_37/lib/Target/AMDGPU/SIISelLowering.cpp?rev=253236&r1=253235&r2=253236&view=diff
==============================================================================
--- llvm/branches/release_37/lib/Target/AMDGPU/SIISelLowering.cpp (original)
+++ llvm/branches/release_37/lib/Target/AMDGPU/SIISelLowering.cpp Mon Nov 16
11:23:34 2015
@@ -2253,10 +2253,8 @@ MachineSDNode *SITargetLowering::buildSc
SDValue Ptr) const {
const SIInstrInfo *TII =
static_cast<const SIInstrInfo *>(Subtarget->getInstrInfo());
- uint64_t Rsrc = TII->getDefaultRsrcDataFormat() | AMDGPU::RSRC_TID_ENABLE |
- 0xffffffff; // Size
- return buildRSRC(DAG, DL, Ptr, 0, Rsrc);
+ return buildRSRC(DAG, DL, Ptr, 0, TII->getScratchRsrcWords23());
}
SDValue SITargetLowering::CreateLiveInRegister(SelectionDAG &DAG,
Modified: llvm/branches/release_37/lib/Target/AMDGPU/SIInstrInfo.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_37/lib/Target/AMDGPU/SIInstrInfo.cpp?rev=253236&r1=253235&r2=253236&view=diff
==============================================================================
--- llvm/branches/release_37/lib/Target/AMDGPU/SIInstrInfo.cpp (original)
+++ llvm/branches/release_37/lib/Target/AMDGPU/SIInstrInfo.cpp Mon Nov 16
11:23:34 2015
@@ -2778,3 +2778,16 @@ uint64_t SIInstrInfo::getDefaultRsrcData
return RsrcDataFormat;
}
+
+uint64_t SIInstrInfo::getScratchRsrcWords23() const {
+ uint64_t Rsrc23 = getDefaultRsrcDataFormat() |
+ AMDGPU::RSRC_TID_ENABLE |
+ 0xffffffff; // Size;
+
+ // If TID_ENABLE is set, DATA_FORMAT specifies stride bits [14:17].
+ // Clear them unless we want a huge stride.
+ if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS)
+ Rsrc23 &= ~AMDGPU::RSRC_DATA_FORMAT;
+
+ return Rsrc23;
+}
Modified: llvm/branches/release_37/lib/Target/AMDGPU/SIInstrInfo.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_37/lib/Target/AMDGPU/SIInstrInfo.h?rev=253236&r1=253235&r2=253236&view=diff
==============================================================================
--- llvm/branches/release_37/lib/Target/AMDGPU/SIInstrInfo.h (original)
+++ llvm/branches/release_37/lib/Target/AMDGPU/SIInstrInfo.h Mon Nov 16
11:23:34 2015
@@ -353,7 +353,7 @@ public:
}
uint64_t getDefaultRsrcDataFormat() const;
-
+ uint64_t getScratchRsrcWords23() const;
};
namespace AMDGPU {
Modified: llvm/branches/release_37/lib/Target/AMDGPU/SIPrepareScratchRegs.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_37/lib/Target/AMDGPU/SIPrepareScratchRegs.cpp?rev=253236&r1=253235&r2=253236&view=diff
==============================================================================
--- llvm/branches/release_37/lib/Target/AMDGPU/SIPrepareScratchRegs.cpp
(original)
+++ llvm/branches/release_37/lib/Target/AMDGPU/SIPrepareScratchRegs.cpp Mon Nov
16 11:23:34 2015
@@ -135,8 +135,7 @@ bool SIPrepareScratchRegs::runOnMachineF
unsigned ScratchRsrcReg =
RS.scavengeRegister(&AMDGPU::SReg_128RegClass, 0);
- uint64_t Rsrc = AMDGPU::RSRC_DATA_FORMAT | AMDGPU::RSRC_TID_ENABLE |
- 0xffffffff; // Size
+ uint64_t Rsrc23 = TII->getScratchRsrcWords23();
unsigned Rsrc0 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub0);
unsigned Rsrc1 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub1);
@@ -152,11 +151,11 @@ bool SIPrepareScratchRegs::runOnMachineF
.addReg(ScratchRsrcReg, RegState::ImplicitDefine);
BuildMI(MBB, I, DL, TII->get(AMDGPU::S_MOV_B32), Rsrc2)
- .addImm(Rsrc & 0xffffffff)
+ .addImm(Rsrc23 & 0xffffffff)
.addReg(ScratchRsrcReg, RegState::ImplicitDefine);
BuildMI(MBB, I, DL, TII->get(AMDGPU::S_MOV_B32), Rsrc3)
- .addImm(Rsrc >> 32)
+ .addImm(Rsrc23 >> 32)
.addReg(ScratchRsrcReg, RegState::ImplicitDefine);
// Scratch Offset
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