================
@@ -760,6 +772,61 @@ def test_riscv64_regs(self):
self.expect("register read --all")
+ @skipIfLLVMTargetMissing("RISCV")
----------------
DavidSpickett wrote:
AArch64 has been saved from this problem by a lot of the new register state
being weird enough it doesn't fit in this test very well. So for example
scalable matrix extension ended up in
`lldb/test/API/linux/aarch64/sme_core_file/TestAArch64LinuxSMECoreFile.py`.
But adding basics like FP here in this file is fine.
https://github.com/llvm/llvm-project/pull/104547
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