================
@@ -34,6 +34,8 @@ def check_first_register_readable(test_case):
test_case.expect("register read r0", substrs=["r0 = 0x"])
elif arch in ["powerpc64le"]:
test_case.expect("register read r0", substrs=["r0 = 0x"])
+ elif arch in ["rv64gc"]:
----------------
dlav-sc wrote:
I have finally decided to add simple regexp, so it's going to work with any
riscv target, not only `rv64gc`.
https://github.com/llvm/llvm-project/pull/99039
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