https://github.com/tmatheson-arm updated
https://github.com/llvm/llvm-project/pull/90987
>From 4b8b776348438847c2eb238dac973e93fe93294e Mon Sep 17 00:00:00 2001
From: Tomas Matheson <tomas.mathe...@arm.com>
Date: Mon, 29 Apr 2024 19:57:17 +0100
Subject: [PATCH 1/3] [AArch64] move extension information into tablgen
Generate target features and FMVExtensions from tablegen.
Use MArchName/ArchKindEnumSpelling to avoid renamings.
Cases where there is simply a case difference are handled by
consistently uppercasing the AEK_ name in the emitted code.
Remove some Extensions which were not needed.
These had AEK entries but were never actually used for anything.
They are not present in Extensions[] data.
---
.../command-disassemble-aarch64-extensions.s | 2 +-
.../llvm/TargetParser/AArch64TargetParser.h | 139 +----------
llvm/lib/Target/AArch64/AArch64Features.td | 216 ++++++++++++++----
.../TargetParser/TargetParserTest.cpp | 8 +-
llvm/utils/TableGen/ARMTargetDefEmitter.cpp | 60 ++++-
5 files changed, 236 insertions(+), 189 deletions(-)
diff --git a/lldb/test/Shell/Commands/command-disassemble-aarch64-extensions.s
b/lldb/test/Shell/Commands/command-disassemble-aarch64-extensions.s
index e154f544e7cc6e..685d0a84ec2896 100644
--- a/lldb/test/Shell/Commands/command-disassemble-aarch64-extensions.s
+++ b/lldb/test/Shell/Commands/command-disassemble-aarch64-extensions.s
@@ -59,7 +59,7 @@ fn:
bdep z0.b, z1.b, z31.b // AEK_SVE2BITPERM
rax1 z0.d, z0.d, z0.d // AEK_SVE2SHA3
sm4e z0.s, z0.s, z0.s // AEK_SVE2SM4
- addqv v0.8h, p0, z0.h // AEK_SVE2p1 / AEK_SME2p1
+ addqv v0.8h, p0, z0.h // AEK_SVE2P1 / AEK_SME2P1
rcwswp x0, x1, [x2] // AEK_THE
tcommit // AEK_TME
lbl:
diff --git a/llvm/include/llvm/TargetParser/AArch64TargetParser.h
b/llvm/include/llvm/TargetParser/AArch64TargetParser.h
index 04fbaf07adfbcb..1124420daf8d80 100644
--- a/llvm/include/llvm/TargetParser/AArch64TargetParser.h
+++ b/llvm/include/llvm/TargetParser/AArch64TargetParser.h
@@ -104,29 +104,9 @@ static_assert(FEAT_MAX < 62,
"Number of features in CPUFeatures are limited to 62 entries");
// Each ArchExtKind correponds directly to a possible -target-feature.
-enum ArchExtKind : unsigned {
- AEK_NONE = 1,
-#define ARM_EXTENSION(NAME, ENUM) ENUM,
+#define EMIT_ARCHEXTKIND_ENUM
#include "llvm/TargetParser/AArch64TargetParserDef.inc"
- AEK_NUM_EXTENSIONS,
-
- // FIXME temporary fixes for inconsistent naming.
- AEK_F32MM = AEK_MATMULFP32,
- AEK_F64MM = AEK_MATMULFP64,
- AEK_FCMA = AEK_COMPLXNUM,
- AEK_FP = AEK_FPARMV8,
- AEK_FP16 = AEK_FULLFP16,
- AEK_I8MM = AEK_MATMULINT8,
- AEK_JSCVT = AEK_JS,
- AEK_PROFILE = AEK_SPE,
- AEK_RASv2 = AEK_RASV2,
- AEK_RAND = AEK_RANDGEN,
- AEK_SIMD = AEK_NEON,
- AEK_SME2p1 = AEK_SME2P1,
- AEK_SVE2p1 = AEK_SVE2P1,
- AEK_SME_LUTv2 = AEK_SME_LUTV2,
-};
using ExtensionBitset = Bitset<AEK_NUM_EXTENSIONS>;
// Represents an extension that can be enabled with -march=<arch>+<extension>.
@@ -148,111 +128,8 @@ struct ExtensionInfo {
1000; // Maximum priority for FMV feature
};
-// NOTE: If adding a new extension here, consider adding it to ExtensionMap
-// in AArch64AsmParser too, if supported as an extension name by binutils.
-// clang-format off
-inline constexpr ExtensionInfo Extensions[] = {
- {"aes", AArch64::AEK_AES, "+aes", "-aes", FEAT_AES, "+fp-armv8,+neon",
150},
- {"b16b16", AArch64::AEK_B16B16, "+b16b16", "-b16b16", FEAT_INIT, "", 0},
- {"bf16", AArch64::AEK_BF16, "+bf16", "-bf16", FEAT_BF16, "+bf16", 280},
- {"brbe", AArch64::AEK_BRBE, "+brbe", "-brbe", FEAT_INIT, "", 0},
- {"bti", AArch64::AEK_NONE, {}, {}, FEAT_BTI, "+bti", 510},
- {"crc", AArch64::AEK_CRC, "+crc", "-crc", FEAT_CRC, "+crc", 110},
- {"crypto", AArch64::AEK_CRYPTO, "+crypto", "-crypto", FEAT_INIT,
"+aes,+sha2", 0},
- {"cssc", AArch64::AEK_CSSC, "+cssc", "-cssc", FEAT_INIT, "", 0},
- {"d128", AArch64::AEK_D128, "+d128", "-d128", FEAT_INIT, "", 0},
- {"dgh", AArch64::AEK_NONE, {}, {}, FEAT_DGH, "", 260},
- {"dit", AArch64::AEK_NONE, {}, {}, FEAT_DIT, "+dit", 180},
- {"dotprod", AArch64::AEK_DOTPROD, "+dotprod", "-dotprod", FEAT_DOTPROD,
"+dotprod,+fp-armv8,+neon", 104},
- {"dpb", AArch64::AEK_NONE, {}, {}, FEAT_DPB, "+ccpp", 190},
- {"dpb2", AArch64::AEK_NONE, {}, {}, FEAT_DPB2, "+ccpp,+ccdp", 200},
- {"ebf16", AArch64::AEK_NONE, {}, {}, FEAT_EBF16, "+bf16", 290},
- {"f32mm", AArch64::AEK_F32MM, "+f32mm", "-f32mm", FEAT_SVE_F32MM,
"+sve,+f32mm,+fullfp16,+fp-armv8,+neon", 350},
- {"f64mm", AArch64::AEK_F64MM, "+f64mm", "-f64mm", FEAT_SVE_F64MM,
"+sve,+f64mm,+fullfp16,+fp-armv8,+neon", 360},
- {"fcma", AArch64::AEK_FCMA, "+complxnum", "-complxnum", FEAT_FCMA,
"+fp-armv8,+neon,+complxnum", 220},
- {"flagm", AArch64::AEK_FLAGM, "+flagm", "-flagm", FEAT_FLAGM, "+flagm",
20},
- {"flagm2", AArch64::AEK_NONE, {}, {}, FEAT_FLAGM2, "+flagm,+altnzcv", 30},
- {"fp", AArch64::AEK_FP, "+fp-armv8", "-fp-armv8", FEAT_FP,
"+fp-armv8,+neon", 90},
- {"fp16", AArch64::AEK_FP16, "+fullfp16", "-fullfp16", FEAT_FP16,
"+fullfp16,+fp-armv8,+neon", 170},
- {"fp16fml", AArch64::AEK_FP16FML, "+fp16fml", "-fp16fml", FEAT_FP16FML,
"+fp16fml,+fullfp16,+fp-armv8,+neon", 175},
- {"frintts", AArch64::AEK_NONE, {}, {}, FEAT_FRINTTS, "+fptoint", 250},
- {"hbc", AArch64::AEK_HBC, "+hbc", "-hbc", FEAT_INIT, "", 0},
- {"i8mm", AArch64::AEK_I8MM, "+i8mm", "-i8mm", FEAT_I8MM, "+i8mm", 270},
- {"ite", AArch64::AEK_ITE, "+ite", "-ite", FEAT_INIT, "", 0},
- {"jscvt", AArch64::AEK_JSCVT, "+jsconv", "-jsconv", FEAT_JSCVT,
"+fp-armv8,+neon,+jsconv", 210},
- {"ls64_accdata", AArch64::AEK_NONE, {}, {}, FEAT_LS64_ACCDATA, "+ls64",
540},
- {"ls64_v", AArch64::AEK_NONE, {}, {}, FEAT_LS64_V, "", 530},
- {"ls64", AArch64::AEK_LS64, "+ls64", "-ls64", FEAT_LS64, "", 520},
- {"lse", AArch64::AEK_LSE, "+lse", "-lse", FEAT_LSE, "+lse", 80},
- {"lse128", AArch64::AEK_LSE128, "+lse128", "-lse128", FEAT_INIT, "", 0},
- {"memtag", AArch64::AEK_MTE, "+mte", "-mte", FEAT_MEMTAG, "", 440},
- {"memtag2", AArch64::AEK_NONE, {}, {}, FEAT_MEMTAG2, "+mte", 450},
- {"memtag3", AArch64::AEK_NONE, {}, {}, FEAT_MEMTAG3, "+mte", 460},
- {"mops", AArch64::AEK_MOPS, "+mops", "-mops", FEAT_MOPS, "+mops", 650},
- {"pauth", AArch64::AEK_PAUTH, "+pauth", "-pauth", FEAT_INIT, "", 0},
- {"pmull", AArch64::AEK_NONE, {}, {}, FEAT_PMULL, "+aes,+fp-armv8,+neon",
160},
- {"pmuv3", AArch64::AEK_PERFMON, "+perfmon", "-perfmon", FEAT_INIT, "", 0},
- {"predres", AArch64::AEK_PREDRES, "+predres", "-predres", FEAT_PREDRES,
"+predres", 480},
- {"predres2", AArch64::AEK_SPECRES2, "+specres2", "-specres2", FEAT_INIT,
"", 0},
- {"profile", AArch64::AEK_PROFILE, "+spe", "-spe", FEAT_INIT, "", 0},
- {"ras", AArch64::AEK_RAS, "+ras", "-ras", FEAT_INIT, "", 0},
- {"rasv2", AArch64::AEK_RASv2, "+rasv2", "-rasv2", FEAT_INIT, "", 0},
- {"rcpc", AArch64::AEK_RCPC, "+rcpc", "-rcpc", FEAT_RCPC, "+rcpc", 230},
- {"rcpc2", AArch64::AEK_NONE, {}, {}, FEAT_RCPC2, "+rcpc", 240},
- {"rcpc3", AArch64::AEK_RCPC3, "+rcpc3", "-rcpc3", FEAT_RCPC3,
"+rcpc,+rcpc3", 241},
- {"rdm", AArch64::AEK_RDM, "+rdm", "-rdm", FEAT_RDM,
"+rdm,+fp-armv8,+neon", 108},
- {"rng", AArch64::AEK_RAND, "+rand", "-rand", FEAT_RNG, "+rand", 10},
- {"rpres", AArch64::AEK_NONE, {}, {}, FEAT_RPRES, "", 300},
- {"sb", AArch64::AEK_SB, "+sb", "-sb", FEAT_SB, "+sb", 470},
- {"sha1", AArch64::AEK_NONE, {}, {}, FEAT_SHA1, "+fp-armv8,+neon", 120},
- {"sha2", AArch64::AEK_SHA2, "+sha2", "-sha2", FEAT_SHA2,
"+sha2,+fp-armv8,+neon", 130},
- {"sha3", AArch64::AEK_SHA3, "+sha3", "-sha3", FEAT_SHA3,
"+sha3,+sha2,+fp-armv8,+neon", 140},
- {"simd", AArch64::AEK_SIMD, "+neon", "-neon", FEAT_SIMD,
"+fp-armv8,+neon", 100},
- {"sm4", AArch64::AEK_SM4, "+sm4", "-sm4", FEAT_SM4,
"+sm4,+fp-armv8,+neon", 106},
- {"sme-f16f16", AArch64::AEK_SMEF16F16, "+sme-f16f16", "-sme-f16f16",
FEAT_INIT, "+sme2,+sme-f16f16", 0},
- {"sme-f64f64", AArch64::AEK_SMEF64F64, "+sme-f64f64", "-sme-f64f64",
FEAT_SME_F64, "+sme,+sme-f64f64,+bf16", 560},
- {"sme-i16i64", AArch64::AEK_SMEI16I64, "+sme-i16i64", "-sme-i16i64",
FEAT_SME_I64, "+sme,+sme-i16i64,+bf16", 570},
- {"sme", AArch64::AEK_SME, "+sme", "-sme", FEAT_SME, "+sme,+bf16", 430},
- {"sme2", AArch64::AEK_SME2, "+sme2", "-sme2", FEAT_SME2,
"+sme2,+sme,+bf16", 580},
- {"sme2p1", AArch64::AEK_SME2p1, "+sme2p1", "-sme2p1", FEAT_INIT,
"+sme2p1,+sme2,+sme,+bf16", 0},
- {"ssbs", AArch64::AEK_SSBS, "+ssbs", "-ssbs", FEAT_SSBS, "", 490},
- {"ssbs2", AArch64::AEK_NONE, {}, {}, FEAT_SSBS2, "+ssbs", 500},
- {"sve-bf16", AArch64::AEK_NONE, {}, {}, FEAT_SVE_BF16,
"+sve,+bf16,+fullfp16,+fp-armv8,+neon", 320},
- {"sve-ebf16", AArch64::AEK_NONE, {}, {}, FEAT_SVE_EBF16,
"+sve,+bf16,+fullfp16,+fp-armv8,+neon", 330},
- {"sve-i8mm", AArch64::AEK_NONE, {}, {}, FEAT_SVE_I8MM,
"+sve,+i8mm,+fullfp16,+fp-armv8,+neon", 340},
- {"sve", AArch64::AEK_SVE, "+sve", "-sve", FEAT_SVE,
"+sve,+fullfp16,+fp-armv8,+neon", 310},
- {"sve2-aes", AArch64::AEK_SVE2AES, "+sve2-aes", "-sve2-aes", FEAT_SVE_AES,
"+sve2,+sve,+sve2-aes,+fullfp16,+fp-armv8,+neon", 380},
- {"sve2-bitperm", AArch64::AEK_SVE2BITPERM, "+sve2-bitperm",
"-sve2-bitperm", FEAT_SVE_BITPERM,
"+sve2,+sve,+sve2-bitperm,+fullfp16,+fp-armv8,+neon", 400},
- {"sve2-pmull128", AArch64::AEK_NONE, {}, {}, FEAT_SVE_PMULL128,
"+sve2,+sve,+sve2-aes,+fullfp16,+fp-armv8,+neon", 390},
- {"sve2-sha3", AArch64::AEK_SVE2SHA3, "+sve2-sha3", "-sve2-sha3",
FEAT_SVE_SHA3, "+sve2,+sve,+sve2-sha3,+fullfp16,+fp-armv8,+neon", 410},
- {"sve2-sm4", AArch64::AEK_SVE2SM4, "+sve2-sm4", "-sve2-sm4", FEAT_SVE_SM4,
"+sve2,+sve,+sve2-sm4,+fullfp16,+fp-armv8,+neon", 420},
- {"sve2", AArch64::AEK_SVE2, "+sve2", "-sve2", FEAT_SVE2,
"+sve2,+sve,+fullfp16,+fp-armv8,+neon", 370},
- {"sve2p1", AArch64::AEK_SVE2p1, "+sve2p1", "-sve2p1", FEAT_INIT,
"+sve2p1,+sve2,+sve,+fullfp16,+fp-armv8,+neon", 0},
- {"the", AArch64::AEK_THE, "+the", "-the", FEAT_INIT, "", 0},
- {"tme", AArch64::AEK_TME, "+tme", "-tme", FEAT_INIT, "", 0},
- {"wfxt", AArch64::AEK_NONE, {}, {}, FEAT_WFXT, "+wfxt", 550},
- {"gcs", AArch64::AEK_GCS, "+gcs", "-gcs", FEAT_INIT, "", 0},
- {"fpmr", AArch64::AEK_FPMR, "+fpmr", "-fpmr", FEAT_INIT, "", 0},
- {"fp8", AArch64::AEK_FP8, "+fp8", "-fp8", FEAT_INIT, "+fpmr", 0},
- {"faminmax", AArch64::AEK_FAMINMAX, "+faminmax", "-faminmax", FEAT_INIT,
"", 0},
- {"fp8fma", AArch64::AEK_FP8FMA, "+fp8fma", "-fp8fma", FEAT_INIT, "+fpmr",
0},
- {"ssve-fp8fma", AArch64::AEK_SSVE_FP8FMA, "+ssve-fp8fma", "-ssve-fp8fma",
FEAT_INIT, "+sme2", 0},
- {"fp8dot2", AArch64::AEK_FP8DOT2, "+fp8dot2", "-fp8dot2", FEAT_INIT, "",
0},
- {"ssve-fp8dot2", AArch64::AEK_SSVE_FP8DOT2, "+ssve-fp8dot2",
"-ssve-fp8dot2", FEAT_INIT, "+sme2", 0},
- {"fp8dot4", AArch64::AEK_FP8DOT4, "+fp8dot4", "-fp8dot4", FEAT_INIT, "",
0},
- {"ssve-fp8dot4", AArch64::AEK_SSVE_FP8DOT4, "+ssve-fp8dot4",
"-ssve-fp8dot4", FEAT_INIT, "+sme2", 0},
- {"lut", AArch64::AEK_LUT, "+lut", "-lut", FEAT_INIT, "", 0},
- {"sme-lutv2", AArch64::AEK_SME_LUTv2, "+sme-lutv2", "-sme-lutv2",
FEAT_INIT, "", 0},
- {"sme-f8f16", AArch64::AEK_SMEF8F16, "+sme-f8f16", "-sme-f8f16",
FEAT_INIT, "+fp8,+sme2", 0},
- {"sme-f8f32", AArch64::AEK_SMEF8F32, "+sme-f8f32", "-sme-f8f32",
FEAT_INIT, "+sme2,+fp8", 0},
- {"sme-fa64", AArch64::AEK_SMEFA64, "+sme-fa64", "-sme-fa64", FEAT_INIT,
"", 0},
- {"cpa", AArch64::AEK_CPA, "+cpa", "-cpa", FEAT_INIT, "", 0},
- {"pauth-lr", AArch64::AEK_PAUTHLR, "+pauth-lr", "-pauth-lr", FEAT_INIT,
"", 0},
- {"tlbiw", AArch64::AEK_TLBIW, "+tlbiw", "-tlbiw", FEAT_INIT, "", 0},
- // Special cases
- {"none", AArch64::AEK_NONE, {}, {}, FEAT_INIT, "",
ExtensionInfo::MaxFMVPriority},
-};
-// clang-format on
+#define EMIT_EXTENSIONS
+#include "llvm/TargetParser/AArch64TargetParserDef.inc"
struct ExtensionSet {
// Set of extensions which are currently enabled.
@@ -328,7 +205,7 @@ inline constexpr ExtensionDependency
ExtensionDependencies[] = {
{AEK_SVE, AEK_SVE2},
{AEK_SVE, AEK_F32MM},
{AEK_SVE, AEK_F64MM},
- {AEK_SVE2, AEK_SVE2p1},
+ {AEK_SVE2, AEK_SVE2P1},
{AEK_SVE2, AEK_SVE2BITPERM},
{AEK_SVE2, AEK_SVE2AES},
{AEK_SVE2, AEK_SVE2SHA3},
@@ -340,7 +217,7 @@ inline constexpr ExtensionDependency
ExtensionDependencies[] = {
{AEK_SME, AEK_SMEF64F64},
{AEK_SME, AEK_SMEI16I64},
{AEK_SME, AEK_SMEFA64},
- {AEK_SME2, AEK_SME2p1},
+ {AEK_SME2, AEK_SME2P1},
{AEK_SME2, AEK_SSVE_FP8FMA},
{AEK_SME2, AEK_SSVE_FP8DOT2},
{AEK_SME2, AEK_SSVE_FP8DOT4},
@@ -350,7 +227,7 @@ inline constexpr ExtensionDependency
ExtensionDependencies[] = {
{AEK_FP8, AEK_SMEF8F32},
{AEK_LSE, AEK_LSE128},
{AEK_PREDRES, AEK_SPECRES2},
- {AEK_RAS, AEK_RASv2},
+ {AEK_RAS, AEK_RASV2},
{AEK_RCPC, AEK_RCPC3},
};
// clang-format on
@@ -429,7 +306,7 @@ inline constexpr ArchInfo ARMV8_7A = { VersionTuple{8, 7},
AProfile, "armv8.7-a
inline constexpr ArchInfo ARMV8_8A = { VersionTuple{8, 8}, AProfile,
"armv8.8-a", "+v8.8a", (ARMV8_7A.DefaultExts |
AArch64::ExtensionBitset({AArch64::AEK_MOPS, AArch64::AEK_HBC}))};
inline constexpr ArchInfo ARMV8_9A = { VersionTuple{8, 9}, AProfile,
"armv8.9-a", "+v8.9a", (ARMV8_8A.DefaultExts |
-
AArch64::ExtensionBitset({AArch64::AEK_SPECRES2, AArch64::AEK_CSSC,
AArch64::AEK_RASv2}))};
+
AArch64::ExtensionBitset({AArch64::AEK_SPECRES2, AArch64::AEK_CSSC,
AArch64::AEK_RASV2}))};
inline constexpr ArchInfo ARMV9A = { VersionTuple{9, 0}, AProfile,
"armv9-a", "+v9a", (ARMV8_5A.DefaultExts |
AArch64::ExtensionBitset({AArch64::AEK_FP16, AArch64::AEK_SVE,
AArch64::AEK_SVE2}))};
inline constexpr ArchInfo ARMV9_1A = { VersionTuple{9, 1}, AProfile,
"armv9.1-a", "+v9.1a", (ARMV9A.DefaultExts |
@@ -438,7 +315,7 @@ inline constexpr ArchInfo ARMV9_2A = { VersionTuple{9, 2},
AProfile, "armv9.2-a
inline constexpr ArchInfo ARMV9_3A = { VersionTuple{9, 3}, AProfile,
"armv9.3-a", "+v9.3a", (ARMV9_2A.DefaultExts |
AArch64::ExtensionBitset({AArch64::AEK_MOPS, AArch64::AEK_HBC}))};
inline constexpr ArchInfo ARMV9_4A = { VersionTuple{9, 4}, AProfile,
"armv9.4-a", "+v9.4a", (ARMV9_3A.DefaultExts |
-
AArch64::ExtensionBitset({AArch64::AEK_SPECRES2, AArch64::AEK_CSSC,
AArch64::AEK_RASv2}))};
+
AArch64::ExtensionBitset({AArch64::AEK_SPECRES2, AArch64::AEK_CSSC,
AArch64::AEK_RASV2}))};
inline constexpr ArchInfo ARMV9_5A = { VersionTuple{9, 5}, AProfile,
"armv9.5-a", "+v9.5a", (ARMV9_4A.DefaultExts |
AArch64::ExtensionBitset({AArch64::AEK_CPA}))};
// For v8-R, we do not enable crypto and align with GCC that enables a more
minimal set of optional architecture extensions.
diff --git a/llvm/lib/Target/AArch64/AArch64Features.td
b/llvm/lib/Target/AArch64/AArch64Features.td
index b6c8e5f1608916..bd5f16d3a5c2c3 100644
--- a/llvm/lib/Target/AArch64/AArch64Features.td
+++ b/llvm/lib/Target/AArch64/AArch64Features.td
@@ -11,42 +11,123 @@
// A SubtargetFeature that can be toggled from the command line, and therefore
// has an AEK_* entry in ArmExtKind.
+//
+// If Function MultiVersioning (FMV) properties are left at their defaults
+// (FEAT_INIT, no dependencies, priority 0) it indiates that this extension is
+// not an FMV feature, but can be enabled via the command line (-march, -mcpu,
+// etc).
+//
+// Conversely if the ArchExtKindSpelling is set to AEK_NONE, this indicates
+// that a feature is FMV-only, and can not be selected on the command line.
+// Such extensions should be added via FMVOnlyExtension.
class Extension<
- string TargetFeatureName, // String used for -target-feature.
+ string TargetFeatureName, // String used for -target-feature and
-march, unless overridden.
string Spelling, // The XYZ in HasXYZ and AEK_XYZ.
string Desc, // Description.
- list<SubtargetFeature> Implies = [] // List of dependent features.
+ list<SubtargetFeature> Implies = [], // List of dependent features.
+ // FMV properties
+ string _FMVBit = "FEAT_INIT", // FEAT_INIT is repurposed to indicate
"not an FMV feature"
+ string _FMVDependencies = "",
+ int _FMVPriority = 0
> : SubtargetFeature<TargetFeatureName, "Has" # Spelling, "true", Desc,
> Implies>
{
string ArchExtKindSpelling = "AEK_" # Spelling; // ArchExtKind enum name.
+
+ // In general, the name written on the command line should match the name
+ // used for -target-feature. However, there are exceptions. Therefore we
+ // add a separate field for this, to allow overriding it. Strongly prefer
+ // not doing so.
+ string MArchName = TargetFeatureName;
+
+ // Function MultiVersioning (FMV) properties
+
+ // A C++ expression giving the number of the bit in the FMV ABI.
+ // Currently this is given as a value from the enum "CPUFeatures".
+ // If this is not set, it indicates that this is not an FMV extension.
+ string FMVBit = _FMVBit;
+
+ // List of features that this feature depends on.
+ // FIXME generate this from Implies.
+ string FMVDependencies = _FMVDependencies;
+
+ // The FMV priority
+ int FMVPriority = _FMVPriority;
+}
+
+// Some extensions are available for FMV but can not be controlled via the
+// command line. These entries:
+// - are SubtargetFeatures, so they have (unused) FieldNames on the subtarget
+// e.g. HasFMVOnlyFEAT_XYZ
+// - have incorrect (empty) Implies fields, because the code that handles FMV
+// ignores these dependencies and looks only at FMVDependencies.
+// - have no description.
+//
+// In the generated data structures for extensions (ExtensionInfo), AEK_NONE is
+// used to indicate that a feature is FMV only. Therefore ArchExtKindSpelling
is
+// manually overridden here.
+class FMVOnlyExtension<string FMVBit, string Name, string Deps, int Priority>
+ : Extension<Name, "FMVOnly"#FMVBit, "", [], FMVBit, Deps, Priority> {
+ let ArchExtKindSpelling = "AEK_NONE"; // AEK_NONE indicates FMV-only
feature
}
+def : FMVOnlyExtension<"FEAT_DGH", "dgh", "", 260>;
+def : FMVOnlyExtension<"FEAT_DIT", "dit", "+dit", 180>;
+def : FMVOnlyExtension<"FEAT_DPB", "dpb", "+ccpp", 190>;
+def : FMVOnlyExtension<"FEAT_DPB2", "dpb2", "+ccpp,+ccdp", 200>;
+def : FMVOnlyExtension<"FEAT_EBF16", "ebf16", "+bf16", 290>;
+def : FMVOnlyExtension<"FEAT_FLAGM2", "flagm2", "+flagm,+altnzcv", 30>;
+def : FMVOnlyExtension<"FEAT_FRINTTS", "frintts", "+fptoint", 250>;
+def : FMVOnlyExtension<"FEAT_LS64_ACCDATA", "ls64_accdata", "+ls64", 540>;
+def : FMVOnlyExtension<"FEAT_LS64_V", "ls64_v", "", 530>;
+def : FMVOnlyExtension<"FEAT_MEMTAG2", "memtag2", "+mte", 450>;
+def : FMVOnlyExtension<"FEAT_MEMTAG3", "memtag3", "+mte", 460>;
+def : FMVOnlyExtension<"FEAT_PMULL", "pmull", "+aes,+fp-armv8,+neon", 160>;
+def : FMVOnlyExtension<"FEAT_RCPC2", "rcpc2", "+rcpc", 240>;
+def : FMVOnlyExtension<"FEAT_RPRES", "rpres", "", 300>;
+def : FMVOnlyExtension<"FEAT_SHA1", "sha1", "+fp-armv8,+neon", 120>;
+def : FMVOnlyExtension<"FEAT_SSBS2", "ssbs2", "+ssbs", 500>;
+def : FMVOnlyExtension<"FEAT_SVE_BF16", "sve-bf16",
"+sve,+bf16,+fullfp16,+fp-armv8,+neon", 320>;
+def : FMVOnlyExtension<"FEAT_SVE_EBF16", "sve-ebf16",
"+sve,+bf16,+fullfp16,+fp-armv8,+neon", 330>;
+def : FMVOnlyExtension<"FEAT_SVE_I8MM", "sve-i8mm",
"+sve,+i8mm,+fullfp16,+fp-armv8,+neon", 340>;
+def : FMVOnlyExtension<"FEAT_SVE_PMULL128", "sve2-pmull128",
"+sve2,+sve,+sve2-aes,+fullfp16,+fp-armv8,+neon", 390>;
+def : FMVOnlyExtension<"FEAT_WFXT", "wfxt", "+wfxt", 550>;
+
+
// Each SubtargetFeature which corresponds to an Arm Architecture feature
should
// be annotated with the respective FEAT_ feature name from the Architecture
// Reference Manual. If a SubtargetFeature enables instructions from multiple
// Arm Architecture Features, it should list all the relevant features. Not all
// FEAT_ features have a corresponding SubtargetFeature.
-def FeatureFPARMv8 : Extension<"fp-armv8", "FPARMv8", "Enable ARMv8
(FEAT_FP)">;
+let ArchExtKindSpelling = "AEK_FP", MArchName = "fp" in
+def FeatureFPARMv8 : Extension<"fp-armv8", "FPARMv8",
+ "Enable ARMv8 (FEAT_FP)", [],
+ "FEAT_FP", "+fp-armv8,+neon", 90>;
+let ArchExtKindSpelling = "AEK_SIMD", MArchName = "simd" in
def FeatureNEON : Extension<"neon", "NEON",
- "Enable Advanced SIMD instructions (FEAT_AdvSIMD)", [FeatureFPARMv8]>;
+ "Enable Advanced SIMD instructions (FEAT_AdvSIMD)", [FeatureFPARMv8],
+ "FEAT_SIMD", "+fp-armv8,+neon", 100>;
def FeatureSM4 : Extension<
"sm4", "SM4",
- "Enable SM3 and SM4 support (FEAT_SM4, FEAT_SM3)", [FeatureNEON]>;
+ "Enable SM3 and SM4 support (FEAT_SM4, FEAT_SM3)", [FeatureNEON],
+ "FEAT_SM4", "+sm4,+fp-armv8,+neon", 106>;
def FeatureSHA2 : Extension<
"sha2", "SHA2",
- "Enable SHA1 and SHA256 support (FEAT_SHA1, FEAT_SHA256)", [FeatureNEON]>;
+ "Enable SHA1 and SHA256 support (FEAT_SHA1, FEAT_SHA256)", [FeatureNEON],
+ "FEAT_SHA2", "+sha2,+fp-armv8,+neon", 130>;
def FeatureSHA3 : Extension<
"sha3", "SHA3",
- "Enable SHA512 and SHA3 support (FEAT_SHA3, FEAT_SHA512)", [FeatureNEON,
FeatureSHA2]>;
+ "Enable SHA512 and SHA3 support (FEAT_SHA3, FEAT_SHA512)", [FeatureNEON,
FeatureSHA2],
+ "FEAT_SHA3", "+sha3,+sha2,+fp-armv8,+neon", 140>;
def FeatureAES : Extension<
"aes", "AES",
- "Enable AES support (FEAT_AES, FEAT_PMULL)", [FeatureNEON]>;
+ "Enable AES support (FEAT_AES, FEAT_PMULL)", [FeatureNEON],
+ "FEAT_AES", "+fp-armv8,+neon", 150>;
// Crypto has been split up and any combination is now valid (see the
// crypto definitions above). Also, crypto is now context sensitive:
@@ -60,7 +141,8 @@ def FeatureCrypto : Extension<"crypto", "Crypto",
"Enable cryptographic instructions", [FeatureNEON, FeatureSHA2, FeatureAES]>;
def FeatureCRC : Extension<"crc", "CRC",
- "Enable ARMv8 CRC-32 checksum instructions (FEAT_CRC32)">;
+ "Enable ARMv8 CRC-32 checksum instructions (FEAT_CRC32)", [],
+ "FEAT_CRC", "+crc", 110>;
def FeatureRAS : Extension<"ras", "RAS",
"Enable ARMv8 Reliability, Availability and Serviceability Extensions
(FEAT_RAS, FEAT_RASv1p1)">;
@@ -70,7 +152,8 @@ def FeatureRASv2 : Extension<"rasv2", "RASv2",
[FeatureRAS]>;
def FeatureLSE : Extension<"lse", "LSE",
- "Enable ARMv8.1 Large System Extension (LSE) atomic instructions
(FEAT_LSE)">;
+ "Enable ARMv8.1 Large System Extension (LSE) atomic instructions
(FEAT_LSE)", [],
+ "FEAT_LSE", "+lse", 80>;
def FeatureLSE2 : SubtargetFeature<"lse2", "HasLSE2", "true",
"Enable ARMv8.4 Large System Extension 2 (LSE2) atomicity rules
(FEAT_LSE2)">;
@@ -83,7 +166,8 @@ def FeatureFMV : SubtargetFeature<"fmv", "HasFMV", "true",
def FeatureRDM : Extension<"rdm", "RDM",
"Enable ARMv8.1 Rounding Double Multiply Add/Subtract instructions
(FEAT_RDM)",
- [FeatureNEON]>;
+ [FeatureNEON],
+ "FEAT_RDM", "+rdm,+fp-armv8,+neon", 108>;
def FeaturePAN : SubtargetFeature<
"pan", "HasPAN", "true",
@@ -102,15 +186,20 @@ def FeatureVH : SubtargetFeature<"vh", "HasVH", "true",
// This SubtargetFeature is special. It controls only whether codegen will turn
// `llvm.readcyclecounter()` into an access to a PMUv3 System Register. The
// `FEAT_PMUv3*` system registers are always available for
assembly/disassembly.
+let MArchName = "pmuv3" in
def FeaturePerfMon : Extension<"perfmon", "PerfMon",
"Enable Code Generation for ARMv8 PMUv3 Performance Monitors extension
(FEAT_PMUv3)">;
+let ArchExtKindSpelling = "AEK_FP16", MArchName = "fp16" in
def FeatureFullFP16 : Extension<"fullfp16", "FullFP16",
- "Full FP16 (FEAT_FP16)", [FeatureFPARMv8]>;
+ "Full FP16 (FEAT_FP16)", [FeatureFPARMv8],
+ "FEAT_FP16", "+fullfp16,+fp-armv8,+neon", 170>;
def FeatureFP16FML : Extension<"fp16fml", "FP16FML",
- "Enable FP16 FML instructions (FEAT_FHM)", [FeatureFullFP16]>;
+ "Enable FP16 FML instructions (FEAT_FHM)", [FeatureFullFP16],
+ "FEAT_FP16FML", "+fp16fml,+fullfp16,+fp-armv8,+neon", 175>;
+let ArchExtKindSpelling = "AEK_PROFILE", MArchName = "profile" in
def FeatureSPE : Extension<"spe", "SPE",
"Enable Statistical Profiling extension (FEAT_SPE)">;
@@ -127,7 +216,8 @@ def FeatureCCPP : SubtargetFeature<"ccpp", "HasCCPP",
"true", "Enable v8.2 data Cache Clean to Point of Persistence (FEAT_DPB)"
>;
def FeatureSVE : Extension<"sve", "SVE",
- "Enable Scalable Vector Extension (SVE) instructions (FEAT_SVE)",
[FeatureFullFP16]>;
+ "Enable Scalable Vector Extension (SVE) instructions (FEAT_SVE)",
[FeatureFullFP16],
+ "FEAT_SVE", "+sve,+fullfp16,+fp-armv8,+neon", 310>;
def FeatureFPMR : Extension<"fpmr", "FPMR",
"Enable FPMR Register (FEAT_FPMR)">;
@@ -157,27 +247,33 @@ def FeatureUseScalarIncVL :
SubtargetFeature<"use-scalar-inc-vl",
"UseScalarIncVL", "true", "Prefer inc/dec over add+cnt">;
def FeatureBF16 : Extension<"bf16", "BF16",
- "Enable BFloat16 Extension (FEAT_BF16)" >;
+ "Enable BFloat16 Extension (FEAT_BF16)", [],
+ "FEAT_BF16", "+bf16", 280>;
def FeatureNoSVEFPLD1R : SubtargetFeature<"no-sve-fp-ld1r",
"NoSVEFPLD1R", "true", "Avoid using LD1RX instructions for FP">;
def FeatureSVE2 : Extension<"sve2", "SVE2",
"Enable Scalable Vector Extension 2 (SVE2) instructions (FEAT_SVE2)",
- [FeatureSVE, FeatureUseScalarIncVL]>;
+ [FeatureSVE, FeatureUseScalarIncVL],
+ "FEAT_SVE2", "+sve2,+sve,+fullfp16,+fp-armv8,+neon", 370>;
def FeatureSVE2AES : Extension<"sve2-aes", "SVE2AES",
"Enable AES SVE2 instructions (FEAT_SVE_AES, FEAT_SVE_PMULL128)",
- [FeatureSVE2, FeatureAES]>;
+ [FeatureSVE2, FeatureAES],
+ "FEAT_SVE_AES", "+sve2,+sve,+sve2-aes,+fullfp16,+fp-armv8,+neon", 380>;
def FeatureSVE2SM4 : Extension<"sve2-sm4", "SVE2SM4",
- "Enable SM4 SVE2 instructions (FEAT_SVE_SM4)", [FeatureSVE2, FeatureSM4]>;
+ "Enable SM4 SVE2 instructions (FEAT_SVE_SM4)", [FeatureSVE2, FeatureSM4],
+ "FEAT_SVE_SM4", "+sve2,+sve,+sve2-sm4,+fullfp16,+fp-armv8,+neon", 420>;
def FeatureSVE2SHA3 : Extension<"sve2-sha3", "SVE2SHA3",
- "Enable SHA3 SVE2 instructions (FEAT_SVE_SHA3)", [FeatureSVE2, FeatureSHA3]>;
+ "Enable SHA3 SVE2 instructions (FEAT_SVE_SHA3)", [FeatureSVE2, FeatureSHA3],
+ "FEAT_SVE_SHA3", "+sve2,+sve,+sve2-sha3,+fullfp16,+fp-armv8,+neon", 410>;
def FeatureSVE2BitPerm : Extension<"sve2-bitperm", "SVE2BitPerm",
- "Enable bit permutation SVE2 instructions (FEAT_SVE_BitPerm)",
[FeatureSVE2]>;
+ "Enable bit permutation SVE2 instructions (FEAT_SVE_BitPerm)", [FeatureSVE2],
+ "FEAT_SVE_BITPERM", "+sve2,+sve,+sve2-bitperm,+fullfp16,+fp-armv8,+neon",
400>;
def FeatureSVE2p1: Extension<"sve2p1", "SVE2p1",
"Enable Scalable Vector Extension 2.1 instructions", [FeatureSVE2]>;
@@ -315,7 +411,8 @@ def FeatureForce32BitJumpTables
"Force jump table entries to be 32-bits wide except at
MinSize">;
def FeatureRCPC : Extension<"rcpc", "RCPC",
- "Enable support for RCPC extension (FEAT_LRCPC)">;
+ "Enable support for RCPC extension (FEAT_LRCPC)", [],
+ "FEAT_RCPC", "+rcpc", 230>;
def FeatureUseRSqrt : SubtargetFeature<
"use-reciprocal-square-root", "UseRSqrt", "true",
@@ -323,25 +420,30 @@ def FeatureUseRSqrt : SubtargetFeature<
def FeatureDotProd : Extension<
"dotprod", "DotProd",
- "Enable dot product support (FEAT_DotProd)", [FeatureNEON]>;
+ "Enable dot product support (FEAT_DotProd)", [FeatureNEON],
+ "FEAT_DOTPROD", "+dotprod,+fp-armv8,+neon", 104>;
def FeaturePAuth : Extension<
"pauth", "PAuth",
"Enable v8.3-A Pointer Authentication extension (FEAT_PAuth)">;
+let ArchExtKindSpelling = "AEK_JSCVT", MArchName = "jscvt" in
def FeatureJS : Extension<
"jsconv", "JS",
"Enable v8.3-A JavaScript FP conversion instructions (FEAT_JSCVT)",
- [FeatureFPARMv8]>;
+ [FeatureFPARMv8],
+ "FEAT_JSCVT", "+fp-armv8,+neon,+jsconv", 210>;
def FeatureCCIDX : SubtargetFeature<
"ccidx", "HasCCIDX", "true",
"Enable v8.3-A Extend of the CCSIDR number of sets (FEAT_CCIDX)">;
+let ArchExtKindSpelling = "AEK_FCMA", MArchName = "fcma" in
def FeatureComplxNum : Extension<
"complxnum", "ComplxNum",
"Enable v8.3-A Floating-point complex number support (FEAT_FCMA)",
- [FeatureNEON]>;
+ [FeatureNEON],
+ "FEAT_FCMA", "+fp-armv8,+neon,+complxnum", 220>;
def FeatureNV : SubtargetFeature<
"nv", "HasNV", "true",
@@ -378,7 +480,8 @@ def FeatureTLB_RMI : SubtargetFeature<
def FeatureFlagM : Extension<
"flagm", "FlagM",
- "Enable v8.4-A Flag Manipulation Instructions (FEAT_FlagM)">;
+ "Enable v8.4-A Flag Manipulation Instructions (FEAT_FlagM)", [],
+ "FEAT_FLAGM", "+flagm", 20>;
// 8.4 RCPC enchancements: LDAPR & STLR instructions with Immediate Offset
def FeatureRCPC_IMMO : SubtargetFeature<"rcpc-immo", "HasRCPC_IMMO", "true",
@@ -426,30 +529,40 @@ def FeatureSpecRestrict :
SubtargetFeature<"specrestrict", "HasSpecRestrict",
"true", "Enable architectural speculation restriction (FEAT_CSV2_2)">;
def FeatureSB : Extension<"sb", "SB",
- "Enable v8.5 Speculation Barrier (FEAT_SB)" >;
+ "Enable v8.5 Speculation Barrier (FEAT_SB)", [],
+ "FEAT_SB", "+sb", 470>;
def FeatureSSBS : Extension<"ssbs", "SSBS",
- "Enable Speculative Store Bypass Safe bit (FEAT_SSBS, FEAT_SSBS2)" >;
+ "Enable Speculative Store Bypass Safe bit (FEAT_SSBS, FEAT_SSBS2)", [],
+ "FEAT_SSBS", "", 490>;
def FeaturePredRes : Extension<"predres", "PredRes",
- "Enable v8.5a execution and data prediction invalidation instructions
(FEAT_SPECRES)" >;
+ "Enable v8.5a execution and data prediction invalidation instructions
(FEAT_SPECRES)", [],
+ "FEAT_PREDRES", "+predres", 480>;
-def FeatureCacheDeepPersist : Extension<"ccdp", "CCDP",
+def FeatureCacheDeepPersist : SubtargetFeature<"ccdp", "CCDP", "true",
"Enable v8.5 Cache Clean to Point of Deep Persistence (FEAT_DPB2)" >;
+// NOTE: BTI now has posfeat/negfeat, which it didn't before
+let ArchExtKindSpelling = "AEK_NONE" in
def FeatureBranchTargetId : Extension<"bti", "BTI",
- "Enable Branch Target Identification (FEAT_BTI)" >;
+ "Enable Branch Target Identification (FEAT_BTI)", [],
+ "FEAT_BTI", "+bti", 510>;
+let ArchExtKindSpelling = "AEK_RAND", MArchName = "rng" in
def FeatureRandGen : Extension<"rand", "RandGen",
- "Enable Random Number generation instructions (FEAT_RNG)" >;
+ "Enable Random Number generation instructions (FEAT_RNG)", [],
+ "FEAT_RNG", "+rand", 10>;
+let MArchName = "memtag" in
def FeatureMTE : Extension<"mte", "MTE",
- "Enable Memory Tagging Extension (FEAT_MTE, FEAT_MTE2)" >;
+ "Enable Memory Tagging Extension (FEAT_MTE, FEAT_MTE2)", [],
+ "FEAT_MEMTAG", "", 440>;
-def FeatureTRBE : Extension<"trbe", "TRBE",
+def FeatureTRBE : SubtargetFeature<"trbe", "TRBE", "true",
"Enable Trace Buffer Extension (FEAT_TRBE)">;
-def FeatureETE : Extension<"ete", "ETE",
+def FeatureETE : SubtargetFeature<"ete", "ETE", "true",
"Enable Embedded Trace Extension (FEAT_ETE)",
[FeatureTRBE]>;
@@ -461,18 +574,25 @@ def FeatureTaggedGlobals :
SubtargetFeature<"tagged-globals",
"true", "Use an instruction sequence for taking the address of a global "
"that allows a memory tag in the upper address bits">;
+let ArchExtKindSpelling = "AEK_I8MM" in
def FeatureMatMulInt8 : Extension<"i8mm", "MatMulInt8",
- "Enable Matrix Multiply Int8 Extension (FEAT_I8MM)">;
+ "Enable Matrix Multiply Int8 Extension (FEAT_I8MM)", [],
+ "FEAT_I8MM", "+i8mm", 270>;
+let ArchExtKindSpelling = "AEK_F32MM" in
def FeatureMatMulFP32 : Extension<"f32mm", "MatMulFP32",
- "Enable Matrix Multiply FP32 Extension (FEAT_F32MM)", [FeatureSVE]>;
+ "Enable Matrix Multiply FP32 Extension (FEAT_F32MM)", [FeatureSVE],
+ "FEAT_SVE_F32MM", "+sve,+f32mm,+fullfp16,+fp-armv8,+neon", 350>;
+let ArchExtKindSpelling = "AEK_F64MM" in
def FeatureMatMulFP64 : Extension<"f64mm", "MatMulFP64",
- "Enable Matrix Multiply FP64 Extension (FEAT_F64MM)", [FeatureSVE]>;
+ "Enable Matrix Multiply FP64 Extension (FEAT_F64MM)", [FeatureSVE],
+ "FEAT_SVE_F64MM", "+sve,+f64mm,+fullfp16,+fp-armv8,+neon", 360>;
def FeatureXS : SubtargetFeature<"xs", "HasXS",
"true", "Enable Armv8.7-A limited-TLB-maintenance instruction (FEAT_XS)">;
+// FIXME link with FMVExtension?
def FeatureWFxT : SubtargetFeature<"wfxt", "HasWFxT",
"true", "Enable Armv8.7-A WFET and WFIT instruction (FEAT_WFxT)">;
@@ -480,13 +600,15 @@ def FeatureHCX : SubtargetFeature<
"hcx", "HasHCX", "true", "Enable Armv8.7-A HCRX_EL2 system register
(FEAT_HCX)">;
def FeatureLS64 : Extension<"ls64", "LS64",
- "Enable Armv8.7-A LD64B/ST64B Accelerator Extension (FEAT_LS64,
FEAT_LS64_V, FEAT_LS64_ACCDATA)">;
+ "Enable Armv8.7-A LD64B/ST64B Accelerator Extension (FEAT_LS64,
FEAT_LS64_V, FEAT_LS64_ACCDATA)", [],
+ "FEAT_LS64", "", 520>;
def FeatureHBC : Extension<"hbc", "HBC",
"Enable Armv8.8-A Hinted Conditional Branches Extension (FEAT_HBC)">;
def FeatureMOPS : Extension<"mops", "MOPS",
- "Enable Armv8.8-A memcpy and memset acceleration instructions
(FEAT_MOPS)">;
+ "Enable Armv8.8-A memcpy and memset acceleration instructions
(FEAT_MOPS)", [],
+ "FEAT_MOPS", "+mops", 650>;
def FeatureNMI : SubtargetFeature<"nmi", "HasNMI",
"true", "Enable Armv8.8-A Non-maskable Interrupts (FEAT_NMI,
FEAT_GICv3_NMI)">;
@@ -508,19 +630,23 @@ def FeatureRME : SubtargetFeature<"rme", "HasRME",
"true", "Enable Realm Management Extension (FEAT_RME)">;
def FeatureSME : Extension<"sme", "SME",
- "Enable Scalable Matrix Extension (SME) (FEAT_SME)", [FeatureBF16,
FeatureUseScalarIncVL]>;
+ "Enable Scalable Matrix Extension (SME) (FEAT_SME)", [FeatureBF16,
FeatureUseScalarIncVL],
+ "FEAT_SME", "+sme,+bf16", 430>;
def FeatureSMEF64F64 : Extension<"sme-f64f64", "SMEF64F64",
- "Enable Scalable Matrix Extension (SME) F64F64 instructions
(FEAT_SME_F64F64)", [FeatureSME]>;
+ "Enable Scalable Matrix Extension (SME) F64F64 instructions
(FEAT_SME_F64F64)", [FeatureSME],
+ "FEAT_SME_F64", "+sme,+sme-f64f64,+bf16", 560>;
def FeatureSMEI16I64 : Extension<"sme-i16i64", "SMEI16I64",
- "Enable Scalable Matrix Extension (SME) I16I64 instructions
(FEAT_SME_I16I64)", [FeatureSME]>;
+ "Enable Scalable Matrix Extension (SME) I16I64 instructions
(FEAT_SME_I16I64)", [FeatureSME],
+ "FEAT_SME_I64", "+sme,+sme-i16i64,+bf16", 570>;
def FeatureSMEFA64 : Extension<"sme-fa64", "SMEFA64",
"Enable the full A64 instruction set in streaming SVE mode (FEAT_SME_FA64)",
[FeatureSME, FeatureSVE2]>;
def FeatureSME2 : Extension<"sme2", "SME2",
- "Enable Scalable Matrix Extension 2 (SME2) instructions", [FeatureSME]>;
+ "Enable Scalable Matrix Extension 2 (SME2) instructions", [FeatureSME],
+ "FEAT_SME2", "+sme2,+sme,+bf16", 580>;
def FeatureSMEF16F16 : Extension<"sme-f16f16", "SMEF16F16",
"Enable SME non-widening Float16 instructions (FEAT_SME_F16F16)",
[FeatureSME2]>;
@@ -592,6 +718,7 @@ def FeatureCLRBHB : SubtargetFeature<"clrbhb", "HasCLRBHB",
def FeaturePRFM_SLC : SubtargetFeature<"prfm-slc-target", "HasPRFM_SLC",
"true", "Enable SLC target for PRFM instruction">;
+let MArchName = "predres2" in
def FeatureSPECRES2 : Extension<"specres2", "SPECRES2",
"Enable Speculation Restriction Instruction (FEAT_SPECRES2)",
[FeaturePredRes]>;
@@ -605,7 +732,8 @@ def FeatureITE : Extension<"ite", "ITE",
def FeatureRCPC3 : Extension<"rcpc3", "RCPC3",
"Enable Armv8.9-A RCPC instructions for A64 and Advanced SIMD and
floating-point instruction set (FEAT_LRCPC3)",
- [FeatureRCPC_IMMO]>;
+ [FeatureRCPC_IMMO],
+ "FEAT_RCPC3", "+rcpc,+rcpc3", 241>;
def FeatureTHE : Extension<"the", "THE",
"Enable Armv8.9-A Translation Hardening Extension (FEAT_THE)">;
diff --git a/llvm/unittests/TargetParser/TargetParserTest.cpp
b/llvm/unittests/TargetParser/TargetParserTest.cpp
index 816aea44a9bc51..779211dcb440bd 100644
--- a/llvm/unittests/TargetParser/TargetParserTest.cpp
+++ b/llvm/unittests/TargetParser/TargetParserTest.cpp
@@ -1989,19 +1989,19 @@ TEST(TargetParserTest, AArch64ExtensionFeatures) {
AArch64::AEK_SME, AArch64::AEK_SMEF64F64,
AArch64::AEK_SMEI16I64, AArch64::AEK_SME2,
AArch64::AEK_HBC, AArch64::AEK_MOPS,
- AArch64::AEK_PERFMON, AArch64::AEK_SVE2p1,
- AArch64::AEK_SME2p1, AArch64::AEK_B16B16,
+ AArch64::AEK_PERFMON, AArch64::AEK_SVE2P1,
+ AArch64::AEK_SME2P1, AArch64::AEK_B16B16,
AArch64::AEK_SMEF16F16, AArch64::AEK_CSSC,
AArch64::AEK_RCPC3, AArch64::AEK_THE,
AArch64::AEK_D128, AArch64::AEK_LSE128,
- AArch64::AEK_SPECRES2, AArch64::AEK_RASv2,
+ AArch64::AEK_SPECRES2, AArch64::AEK_RASV2,
AArch64::AEK_ITE, AArch64::AEK_GCS,
AArch64::AEK_FPMR, AArch64::AEK_FP8,
AArch64::AEK_FAMINMAX, AArch64::AEK_FP8FMA,
AArch64::AEK_SSVE_FP8FMA, AArch64::AEK_FP8DOT2,
AArch64::AEK_SSVE_FP8DOT2, AArch64::AEK_FP8DOT4,
AArch64::AEK_SSVE_FP8DOT4, AArch64::AEK_LUT,
- AArch64::AEK_SME_LUTv2, AArch64::AEK_SMEF8F16,
+ AArch64::AEK_SME_LUTV2, AArch64::AEK_SMEF8F16,
AArch64::AEK_SMEF8F32, AArch64::AEK_SMEFA64,
AArch64::AEK_CPA, AArch64::AEK_PAUTHLR,
AArch64::AEK_TLBIW, AArch64::AEK_JSCVT,
diff --git a/llvm/utils/TableGen/ARMTargetDefEmitter.cpp
b/llvm/utils/TableGen/ARMTargetDefEmitter.cpp
index 05aa146b57159d..43aff2cfaf9f89 100644
--- a/llvm/utils/TableGen/ARMTargetDefEmitter.cpp
+++ b/llvm/utils/TableGen/ARMTargetDefEmitter.cpp
@@ -15,6 +15,7 @@
#include "llvm/ADT/StringSet.h"
#include "llvm/TableGen/Record.h"
#include "llvm/TableGen/TableGenBackend.h"
+#include <cstdint>
using namespace llvm;
@@ -33,6 +34,16 @@ static void EmitARMTargetDef(RecordKeeper &RK, raw_ostream
&OS) {
return Set;
};
+ // Sort the extensions alphabetically, so they don't appear in tablegen
order.
+ std::vector<Record *> SortedExtensions =
+ RK.getAllDerivedDefinitions("Extension");
+ auto Alphabetical = [](Record *A, Record *B) -> bool {
+ const auto MarchA = A->getValueAsString("MArchName");
+ const auto MarchB = B->getValueAsString("MArchName");
+ return MarchA.compare(MarchB) < 0; // A lexographically less than B
+ };
+ std::sort(SortedExtensions.begin(), SortedExtensions.end(), Alphabetical);
+
// The ARMProcFamilyEnum values are initialised by SubtargetFeature defs
// which set the ARMProcFamily field. We can generate the enum from these
defs
// which look like this:
@@ -57,16 +68,47 @@ static void EmitARMTargetDef(RecordKeeper &RK, raw_ostream
&OS) {
OS << "ARM_ARCHITECTURE(" << Arch << ")\n";
OS << "\n#undef ARM_ARCHITECTURE\n\n";
- // Emit information for each defined Extension; used to build ArmExtKind.
- OS << "#ifndef ARM_EXTENSION\n"
- << "#define ARM_EXTENSION(NAME, ENUM)\n"
- << "#endif\n\n";
- for (const Record *Rec : RK.getAllDerivedDefinitions("Extension")) {
- StringRef Name = Rec->getValueAsString("Name");
- std::string Enum = Rec->getValueAsString("ArchExtKindSpelling").upper();
- OS << "ARM_EXTENSION(" << Name << ", " << Enum << ")\n";
+ // Emit the ArchExtKind enum
+ OS << "#ifdef EMIT_ARCHEXTKIND_ENUM\n"
+ << "enum ArchExtKind : unsigned {\n"
+ << " AEK_NONE = 1,\n";
+ for (const Record *Rec : SortedExtensions) {
+ auto AEK = Rec->getValueAsString("ArchExtKindSpelling").upper();
+ if (AEK != "AEK_NONE")
+ OS << " " << AEK << ",\n";
}
- OS << "\n#undef ARM_EXTENSION\n\n";
+ OS << " AEK_NUM_EXTENSIONS\n"
+ << "};\n"
+ << "#undef EMIT_ARCHEXTKIND_ENUM\n"
+ << "#endif // EMIT_ARCHEXTKIND_ENUM\n";
+
+ // Emit information for each defined Extension; used to build ArmExtKind.
+ OS << "#ifdef EMIT_EXTENSIONS\n"
+ << "inline constexpr ExtensionInfo Extensions[] = {\n";
+ for (const Record *Rec : SortedExtensions) {
+ auto AEK = Rec->getValueAsString("ArchExtKindSpelling").upper();
+ OS << " ";
+ OS << "{\"" << Rec->getValueAsString("MArchName") << "\"";
+ OS << ", AArch64::" << AEK;
+ if (AEK == "AEK_NONE") {
+ // HACK: don't emit posfeat/negfeat strings for FMVOnlyExtensions.
+ OS << ", {}, {}";
+ } else {
+ OS << ", \"+" << Rec->getValueAsString("Name") << "\""; // posfeature
+ OS << ", \"-" << Rec->getValueAsString("Name") << "\""; // negfeature
+ }
+ OS << ", " << Rec->getValueAsString("FMVBit");
+ OS << ", \"" << Rec->getValueAsString("FMVDependencies") << "\"";
+ OS << ", " << (uint64_t)Rec->getValueAsInt("FMVPriority");
+ OS << "},\n";
+ };
+ OS << " {\"none\", AArch64::AEK_NONE, {}, {}, FEAT_INIT, \"\", "
+ "ExtensionInfo::MaxFMVPriority},\n";
+ OS << "};\n"
+ << "#undef EMIT_EXTENSIONS\n"
+ << "#endif // EMIT_EXTENSIONS\n"
+ << "\n";
+
}
static TableGen::Emitter::Opt
>From e8bfa2a3d679035d96c5bcbdb6e3fd42c295916e Mon Sep 17 00:00:00 2001
From: Tomas Matheson <tomas.mathe...@arm.com>
Date: Fri, 3 May 2024 18:14:05 +0100
Subject: [PATCH 2/3] Override FMVDependencies where necessary
---
llvm/lib/Target/AArch64/AArch64Features.td | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/llvm/lib/Target/AArch64/AArch64Features.td
b/llvm/lib/Target/AArch64/AArch64Features.td
index bd5f16d3a5c2c3..04deaa8caba350 100644
--- a/llvm/lib/Target/AArch64/AArch64Features.td
+++ b/llvm/lib/Target/AArch64/AArch64Features.td
@@ -137,6 +137,7 @@ def FeatureAES : Extension<
// meaning anymore. We kept the Crypto definition here for backward
// compatibility, and now imply features SHA2 and AES, which was the
// "traditional" meaning of Crypto.
+let FMVDependencies = "+aes,+sha2" in
def FeatureCrypto : Extension<"crypto", "Crypto",
"Enable cryptographic instructions", [FeatureNEON, FeatureSHA2, FeatureAES]>;
@@ -222,6 +223,7 @@ def FeatureSVE : Extension<"sve", "SVE",
def FeatureFPMR : Extension<"fpmr", "FPMR",
"Enable FPMR Register (FEAT_FPMR)">;
+let FMVDependencies = "+fpmr" in
def FeatureFP8 : Extension<"fp8", "FP8",
"Enable FP8 instructions (FEAT_FP8)">;
@@ -275,6 +277,7 @@ def FeatureSVE2BitPerm : Extension<"sve2-bitperm",
"SVE2BitPerm",
"Enable bit permutation SVE2 instructions (FEAT_SVE_BitPerm)", [FeatureSVE2],
"FEAT_SVE_BITPERM", "+sve2,+sve,+sve2-bitperm,+fullfp16,+fp-armv8,+neon",
400>;
+let FMVDependencies = "+sve2p1,+sve2,+sve,+fullfp16,+fp-armv8,+neon" in
def FeatureSVE2p1: Extension<"sve2p1", "SVE2p1",
"Enable Scalable Vector Extension 2.1 instructions", [FeatureSVE2]>;
@@ -648,30 +651,36 @@ def FeatureSME2 : Extension<"sme2", "SME2",
"Enable Scalable Matrix Extension 2 (SME2) instructions", [FeatureSME],
"FEAT_SME2", "+sme2,+sme,+bf16", 580>;
+let FMVDependencies = "+sme2,+sme-f16f16" in
def FeatureSMEF16F16 : Extension<"sme-f16f16", "SMEF16F16",
"Enable SME non-widening Float16 instructions (FEAT_SME_F16F16)",
[FeatureSME2]>;
+let FMVDependencies = "+sme2p1,+sme2,+sme,+bf16" in
def FeatureSME2p1 : Extension<"sme2p1", "SME2p1",
"Enable Scalable Matrix Extension 2.1 (FEAT_SME2p1) instructions",
[FeatureSME2]>;
def FeatureFAMINMAX: Extension<"faminmax", "FAMINMAX",
"Enable FAMIN and FAMAX instructions (FEAT_FAMINMAX)">;
+let FMVDependencies = "+fpmr" in
def FeatureFP8FMA : Extension<"fp8fma", "FP8FMA",
"Enable fp8 multiply-add instructions (FEAT_FP8FMA)">;
+let FMVDependencies = "+sme2" in
def FeatureSSVE_FP8FMA : Extension<"ssve-fp8fma", "SSVE_FP8FMA",
"Enable SVE2 fp8 multiply-add instructions (FEAT_SSVE_FP8FMA)",
[FeatureSME2]>;
def FeatureFP8DOT2: Extension<"fp8dot2", "FP8DOT2",
"Enable fp8 2-way dot instructions (FEAT_FP8DOT2)">;
+let FMVDependencies = "+sme2" in
def FeatureSSVE_FP8DOT2 : Extension<"ssve-fp8dot2", "SSVE_FP8DOT2",
"Enable SVE2 fp8 2-way dot product instructions (FEAT_SSVE_FP8DOT2)",
[FeatureSME2]>;
def FeatureFP8DOT4: Extension<"fp8dot4", "FP8DOT4",
"Enable fp8 4-way dot instructions (FEAT_FP8DOT4)">;
+let FMVDependencies = "+sme2" in
def FeatureSSVE_FP8DOT4 : Extension<"ssve-fp8dot4", "SSVE_FP8DOT4",
"Enable SVE2 fp8 4-way dot product instructions (FEAT_SSVE_FP8DOT4)",
[FeatureSME2]>;
def FeatureLUT: Extension<"lut", "LUT",
@@ -680,9 +689,11 @@ def FeatureLUT: Extension<"lut", "LUT",
def FeatureSME_LUTv2 : Extension<"sme-lutv2", "SME_LUTv2",
"Enable Scalable Matrix Extension (SME) LUTv2 instructions
(FEAT_SME_LUTv2)">;
+let FMVDependencies = "+fp8,+sme2" in
def FeatureSMEF8F16 : Extension<"sme-f8f16", "SMEF8F16",
"Enable Scalable Matrix Extension (SME) F8F16 instructions(FEAT_SME_F8F16)",
[FeatureSME2, FeatureFP8]>;
+let FMVDependencies = "+sme2,+fp8" in
def FeatureSMEF8F32 : Extension<"sme-f8f32", "SMEF8F32",
"Enable Scalable Matrix Extension (SME) F8F32 instructions
(FEAT_SME_F8F32)", [FeatureSME2, FeatureFP8]>;
>From 45f4baf69795dab5988fddbec444384ff670e452 Mon Sep 17 00:00:00 2001
From: Tomas Matheson <tomas.mathe...@arm.com>
Date: Fri, 3 May 2024 18:47:30 +0100
Subject: [PATCH 3/3] clang-format
---
llvm/utils/TableGen/ARMTargetDefEmitter.cpp | 1 -
1 file changed, 1 deletion(-)
diff --git a/llvm/utils/TableGen/ARMTargetDefEmitter.cpp
b/llvm/utils/TableGen/ARMTargetDefEmitter.cpp
index 43aff2cfaf9f89..4a46f2ea95869c 100644
--- a/llvm/utils/TableGen/ARMTargetDefEmitter.cpp
+++ b/llvm/utils/TableGen/ARMTargetDefEmitter.cpp
@@ -108,7 +108,6 @@ static void EmitARMTargetDef(RecordKeeper &RK, raw_ostream
&OS) {
<< "#undef EMIT_EXTENSIONS\n"
<< "#endif // EMIT_EXTENSIONS\n"
<< "\n";
-
}
static TableGen::Emitter::Opt
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