This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
DavidSpickett marked an inline comment as done.
Closed by commit rG6697afe99fb6: [lldb][AArch64] Check SIMD save/restore in SVE
SIMD test (authored by DavidSpickett).
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D157000/new/
https://reviews.llvm.org/D157000
Files:
lldb/test/API/commands/register/register/aarch64_sve_simd_registers/TestSVESIMDRegisters.py
lldb/test/API/commands/register/register/aarch64_sve_simd_registers/main.c
Index:
lldb/test/API/commands/register/register/aarch64_sve_simd_registers/main.c
===================================================================
--- lldb/test/API/commands/register/register/aarch64_sve_simd_registers/main.c
+++ lldb/test/API/commands/register/register/aarch64_sve_simd_registers/main.c
@@ -1,10 +1,11 @@
#include <stdint.h>
#include <sys/prctl.h>
-void write_simd_regs() {
+// base is added to each value. If base = 2, then v0 = 2, v1 = 3, etc.
+void write_simd_regs(unsigned base) {
#define WRITE_SIMD(NUM)
\
asm volatile("MOV v" #NUM ".d[0], %0\n\t"
\
- "MOV v" #NUM ".d[1], %0\n\t" ::"r"(NUM))
+ "MOV v" #NUM ".d[1], %0\n\t" ::"r"(base + NUM))
WRITE_SIMD(0);
WRITE_SIMD(1);
@@ -102,7 +103,7 @@
#endif
// else test plain SIMD access.
- write_simd_regs();
+ write_simd_regs(0);
return verify_simd_regs(); // Set a break point here.
}
Index:
lldb/test/API/commands/register/register/aarch64_sve_simd_registers/TestSVESIMDRegisters.py
===================================================================
---
lldb/test/API/commands/register/register/aarch64_sve_simd_registers/TestSVESIMDRegisters.py
+++
lldb/test/API/commands/register/register/aarch64_sve_simd_registers/TestSVESIMDRegisters.py
@@ -1,6 +1,6 @@
"""
-Test that LLDB correctly reads and writes AArch64 SIMD registers in SVE,
-streaming SVE and normal SIMD modes.
+Test that LLDB correctly reads and writes and restores AArch64 SIMD registers
+in SVE, streaming SVE and normal SIMD modes.
There are a few operating modes and we use different strategies for each:
* Without SVE, in SIMD mode - read the SIMD regset.
@@ -48,6 +48,13 @@
pad = " ".join(["0x00"] * 7)
return "{{0x{:02x} {} 0x{:02x} {}}}".format(n, pad, n, pad)
+ def check_simd_values(self, value_offset):
+ # These are 128 bit registers, so getting them from the API as unsigned
+ # values doesn't work. Check the command output instead.
+ for i in range(32):
+ self.expect("register read v{}".format(i),
+ substrs=[self.make_simd_value(i+value_offset)])
+
def sve_simd_registers_impl(self, mode):
self.skip_if_needed(mode)
@@ -68,12 +75,9 @@
substrs=["stop reason = breakpoint 1."],
)
- # These are 128 bit registers, so getting them from the API as unsigned
- # values doesn't work. Check the command output instead.
- for i in range(32):
- self.expect(
- "register read v{}".format(i),
substrs=[self.make_simd_value(i)]
- )
+ self.check_simd_values(0)
+ self.runCmd("expression write_simd_regs(1)")
+ self.check_simd_values(0)
# Write a new set of values. The kernel will move the program back to
# non-streaming mode here.
@@ -83,10 +87,7 @@
)
# Should be visible within lldb.
- for i in range(32):
- self.expect(
- "register read v{}".format(i), substrs=[self.make_simd_value(i
+ 1)]
- )
+ self.check_simd_values(1)
# The program should agree with lldb.
self.expect("continue", substrs=["exited with status = 0"])
Index: lldb/test/API/commands/register/register/aarch64_sve_simd_registers/main.c
===================================================================
--- lldb/test/API/commands/register/register/aarch64_sve_simd_registers/main.c
+++ lldb/test/API/commands/register/register/aarch64_sve_simd_registers/main.c
@@ -1,10 +1,11 @@
#include <stdint.h>
#include <sys/prctl.h>
-void write_simd_regs() {
+// base is added to each value. If base = 2, then v0 = 2, v1 = 3, etc.
+void write_simd_regs(unsigned base) {
#define WRITE_SIMD(NUM) \
asm volatile("MOV v" #NUM ".d[0], %0\n\t" \
- "MOV v" #NUM ".d[1], %0\n\t" ::"r"(NUM))
+ "MOV v" #NUM ".d[1], %0\n\t" ::"r"(base + NUM))
WRITE_SIMD(0);
WRITE_SIMD(1);
@@ -102,7 +103,7 @@
#endif
// else test plain SIMD access.
- write_simd_regs();
+ write_simd_regs(0);
return verify_simd_regs(); // Set a break point here.
}
Index: lldb/test/API/commands/register/register/aarch64_sve_simd_registers/TestSVESIMDRegisters.py
===================================================================
--- lldb/test/API/commands/register/register/aarch64_sve_simd_registers/TestSVESIMDRegisters.py
+++ lldb/test/API/commands/register/register/aarch64_sve_simd_registers/TestSVESIMDRegisters.py
@@ -1,6 +1,6 @@
"""
-Test that LLDB correctly reads and writes AArch64 SIMD registers in SVE,
-streaming SVE and normal SIMD modes.
+Test that LLDB correctly reads and writes and restores AArch64 SIMD registers
+in SVE, streaming SVE and normal SIMD modes.
There are a few operating modes and we use different strategies for each:
* Without SVE, in SIMD mode - read the SIMD regset.
@@ -48,6 +48,13 @@
pad = " ".join(["0x00"] * 7)
return "{{0x{:02x} {} 0x{:02x} {}}}".format(n, pad, n, pad)
+ def check_simd_values(self, value_offset):
+ # These are 128 bit registers, so getting them from the API as unsigned
+ # values doesn't work. Check the command output instead.
+ for i in range(32):
+ self.expect("register read v{}".format(i),
+ substrs=[self.make_simd_value(i+value_offset)])
+
def sve_simd_registers_impl(self, mode):
self.skip_if_needed(mode)
@@ -68,12 +75,9 @@
substrs=["stop reason = breakpoint 1."],
)
- # These are 128 bit registers, so getting them from the API as unsigned
- # values doesn't work. Check the command output instead.
- for i in range(32):
- self.expect(
- "register read v{}".format(i), substrs=[self.make_simd_value(i)]
- )
+ self.check_simd_values(0)
+ self.runCmd("expression write_simd_regs(1)")
+ self.check_simd_values(0)
# Write a new set of values. The kernel will move the program back to
# non-streaming mode here.
@@ -83,10 +87,7 @@
)
# Should be visible within lldb.
- for i in range(32):
- self.expect(
- "register read v{}".format(i), substrs=[self.make_simd_value(i + 1)]
- )
+ self.check_simd_values(1)
# The program should agree with lldb.
self.expect("continue", substrs=["exited with status = 0"])
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