DavidSpickett updated this revision to Diff 549834.
DavidSpickett added a comment.
Rebase
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D157000/new/
https://reviews.llvm.org/D157000
Files:
lldb/test/API/commands/register/register/aarch64_sve_simd_registers/TestSVESIMDRegisters.py
lldb/test/API/commands/register/register/aarch64_sve_simd_registers/main.c
Index: lldb/test/API/commands/register/register/aarch64_sve_simd_registers/main.c
===================================================================
--- lldb/test/API/commands/register/register/aarch64_sve_simd_registers/main.c
+++ lldb/test/API/commands/register/register/aarch64_sve_simd_registers/main.c
@@ -40,6 +40,45 @@
WRITE_SIMD(31);
}
+void write_simd_regs_expr() {
+#define WRITE_SIMD(NUM) \
+ asm volatile("MOV v" #NUM ".d[0], %0\n\t" \
+ "MOV v" #NUM ".d[1], %0\n\t" ::"r"(NUM + 1))
+
+ WRITE_SIMD(0);
+ WRITE_SIMD(1);
+ WRITE_SIMD(2);
+ WRITE_SIMD(3);
+ WRITE_SIMD(4);
+ WRITE_SIMD(5);
+ WRITE_SIMD(6);
+ WRITE_SIMD(7);
+ WRITE_SIMD(8);
+ WRITE_SIMD(9);
+ WRITE_SIMD(10);
+ WRITE_SIMD(11);
+ WRITE_SIMD(12);
+ WRITE_SIMD(13);
+ WRITE_SIMD(14);
+ WRITE_SIMD(15);
+ WRITE_SIMD(16);
+ WRITE_SIMD(17);
+ WRITE_SIMD(18);
+ WRITE_SIMD(19);
+ WRITE_SIMD(20);
+ WRITE_SIMD(21);
+ WRITE_SIMD(22);
+ WRITE_SIMD(23);
+ WRITE_SIMD(24);
+ WRITE_SIMD(25);
+ WRITE_SIMD(26);
+ WRITE_SIMD(27);
+ WRITE_SIMD(28);
+ WRITE_SIMD(29);
+ WRITE_SIMD(30);
+ WRITE_SIMD(31);
+}
+
unsigned verify_simd_regs() {
uint64_t got_low = 0;
uint64_t got_high = 0;
Index: lldb/test/API/commands/register/register/aarch64_sve_simd_registers/TestSVESIMDRegisters.py
===================================================================
--- lldb/test/API/commands/register/register/aarch64_sve_simd_registers/TestSVESIMDRegisters.py
+++ lldb/test/API/commands/register/register/aarch64_sve_simd_registers/TestSVESIMDRegisters.py
@@ -1,6 +1,6 @@
"""
-Test that LLDB correctly reads and writes AArch64 SIMD registers in SVE,
-streaming SVE and normal SIMD modes.
+Test that LLDB correctly reads and writes and restores AArch64 SIMD registers
+in SVE, streaming SVE and normal SIMD modes.
There are a few operating modes and we use different strategies for each:
* Without SVE, in SIMD mode - read the SIMD regset.
@@ -48,6 +48,13 @@
pad = " ".join(["0x00"] * 7)
return "{{0x{:02x} {} 0x{:02x} {}}}".format(n, pad, n, pad)
+ def check_simd_values(self, value_offset):
+ # These are 128 bit registers, so getting them from the API as unsigned
+ # values doesn't work. Check the command output instead.
+ for i in range(32):
+ self.expect("register read v{}".format(i),
+ substrs=[self.make_simd_value(i+value_offset)])
+
def sve_simd_registers_impl(self, mode):
self.skip_if_needed(mode)
@@ -68,12 +75,9 @@
substrs=["stop reason = breakpoint 1."],
)
- # These are 128 bit registers, so getting them from the API as unsigned
- # values doesn't work. Check the command output instead.
- for i in range(32):
- self.expect(
- "register read v{}".format(i), substrs=[self.make_simd_value(i)]
- )
+ self.check_simd_values(0)
+ self.runCmd("expression write_simd_regs_expr()")
+ self.check_simd_values(0)
# Write a new set of values. The kernel will move the program back to
# non-streaming mode here.
@@ -83,10 +87,7 @@
)
# Should be visible within lldb.
- for i in range(32):
- self.expect(
- "register read v{}".format(i), substrs=[self.make_simd_value(i + 1)]
- )
+ self.check_simd_values(1)
# The program should agree with lldb.
self.expect("continue", substrs=["exited with status = 0"])
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