jasonmolenda added a comment. I have no experience with the linux support so I'm not an ideal person to review, but when I was reading about watchpoints I saw the caveats about SSVE mode and false watchpoint hits so I read through the patch out of curiosity about SME/SSVE. You mention a couple of times that when in SSVE mode, we can only write to the SVE registers and doing so forces the processor out of SSVE Mode. We can read the SSVE registers while in SSVE mode though right?
================ Comment at: lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp:532 // AArch64 register data must contain GPRs, either FPR or SVE registers - // and optional MTE register. Pointer Authentication (PAC) registers are - // read-only and will be skiped. + // (which can be non-streaming, SVE or streaming, SSVE) and optional MTE + // register. Pointer Authentication (PAC) registers are read-only and will be ---------------- it's super minor, but I think you're meaning to describe two states here, but it sounds like four. Maybe "which can be non-streaming (SVE), or streaming (SSVE)" is the best I can come up with. ================ Comment at: lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp:534 + // register. Pointer Authentication (PAC) registers are read-only and will be + // skiped. ---------------- skipped Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D154926/new/ https://reviews.llvm.org/D154926 _______________________________________________ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
