DavidSpickett added inline comments.
================
Comment at:
lldb/test/API/commands/register/register/aarch64_dynamic_regset/TestArm64DynamicRegsets.py:35
+
+ p_value_bytes = ['0xff', '0x55', '0x11', '0x01', '0x00']
+ for i in range(16):
----------------
omjavaid wrote:
> DavidSpickett wrote:
> > Can you explain the logic for the values here?
> P reg sets predicate lanes. P0 will have all lanes set while P5 will have no
> lanes set. These are just random values testing read/write.
I would put that in a comment to save some time for those unfamiliar with SVE.
================
Comment at:
lldb/test/API/commands/register/register/aarch64_dynamic_regset/main.c:31-32
+
+ asm volatile("cpy z0.b, p0/z, #1\n\t");
+ asm volatile("cpy z1.b, p5/z, #2\n\t");
+ asm volatile("cpy z2.b, p10/z, #3\n\t");
----------------
omjavaid wrote:
> DavidSpickett wrote:
> > Same here, is the p0/p5/p10/p15 pattern affecting values used in the test
> > or just for fun? (which isn't a bad thing)
> I copied this from SVE test case that I wrote last year.
>
> P is a predicate register and ptrue/pfalse instruction is used to set a
> predicate lane with a pattern. pattern is decide based on size specifier, b,
> h, s and d.
>
> if size specified is b all lanes will be set to 1. which is needed to set al
> bytes in a Z registers to the specified value.
>
> We are setting p0, p5, p10 and p15 to enable all lanes other p registers are
> not enabling all lanes thats why they were not used as predicate for setting
> Z registers in following lines which set a constant value to Z register byte
> size elements.
I'd put that in a comment. Enough for someone triaging a failure to know what's
arbitrary numbers and what's very specific.
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D96463/new/
https://reviews.llvm.org/D96463
_______________________________________________
lldb-commits mailing list
lldb-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
