================ @@ -0,0 +1,76 @@ +//===-- RegisterInfoPOSIX_riscv32.h -----------------------------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERINFOPOSIX_RISCV32_H +#define LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERINFOPOSIX_RISCV32_H + +#include "RegisterInfoAndSetInterface.h" +#include "lldb/Target/RegisterContext.h" +#include "lldb/Utility/Flags.h" +#include "lldb/lldb-private.h" + +#include <map> + +class RegisterInfoPOSIX_riscv32 + : public lldb_private::RegisterInfoAndSetInterface { +public: + static const lldb_private::RegisterInfo * + GetRegisterInfoPtr(const lldb_private::ArchSpec &target_arch); + static uint32_t + GetRegisterInfoCount(const lldb_private::ArchSpec &target_arch); + +public: + // RISC-V32 register set mask value + enum { + eRegsetMaskDefault = 0, + eRegsetMaskFP = 1, + eRegsetMaskAll = -1, + }; + + struct GPR { + // note: gpr[0] is pc, not x0 ---------------- jasonmolenda wrote:
Yes, x0 aka zero is constant value 0, so they're using that slot of the GPR register file to store the PC internally. The ReadRegister (and WriteRegister if it was implemented) method needs to special case accesses to x0 to return a UInt32(0) because it's not stored in the GPRs. I don't see that part handled by this class (or by `RegisterInfoPOSIX_riscv64` / `RegisterInfos_riscv64.h` which it's inspired by). https://github.com/llvm/llvm-project/pull/115408 _______________________________________________ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
