================ @@ -0,0 +1,76 @@ +//===-- RegisterInfoPOSIX_riscv32.h -----------------------------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERINFOPOSIX_RISCV32_H +#define LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERINFOPOSIX_RISCV32_H + +#include "RegisterInfoAndSetInterface.h" +#include "lldb/Target/RegisterContext.h" +#include "lldb/Utility/Flags.h" +#include "lldb/lldb-private.h" + +#include <map> + +class RegisterInfoPOSIX_riscv32 + : public lldb_private::RegisterInfoAndSetInterface { +public: + static const lldb_private::RegisterInfo * + GetRegisterInfoPtr(const lldb_private::ArchSpec &target_arch); + static uint32_t + GetRegisterInfoCount(const lldb_private::ArchSpec &target_arch); + +public: + // RISC-V32 register set mask value + enum { + eRegsetMaskDefault = 0, + eRegsetMaskFP = 1, + eRegsetMaskAll = -1, + }; + + struct GPR { + // note: gpr[0] is pc, not x0 + uint32_t gpr[32]; + }; + + struct FPR { + uint32_t fpr[32]; + uint32_t fcsr; + }; + + struct VPR { ---------------- jasonmolenda wrote:
I don't see why we're including data store for the VPR vector register, or adding the register definitions below. There are no read or write accesses to these, and it'd prob be less confusing if they weren't listed at all. https://github.com/llvm/llvm-project/pull/115408 _______________________________________________ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
