mohit.bhakkad created this revision.
mohit.bhakkad added reviewers: clayborg, zturner.
mohit.bhakkad added subscribers: jaydeep, bhushan, sagar, nitesh.jain,
lldb-commits.
mohit.bhakkad set the repository for this revision to rL LLVM.
Some machines of an arch may not have all the regs listed for it in RegInfo,
and we get 'E15' as error while reading from such register, i.e. its not
available.
For example MSA registers listed for MIPS are not present in all MIPS boards.
Repository:
rL LLVM
http://reviews.llvm.org/D13859
Files:
test/tools/lldb-server/TestLldbGdbServer.py
Index: test/tools/lldb-server/TestLldbGdbServer.py
===================================================================
--- test/tools/lldb-server/TestLldbGdbServer.py
+++ test/tools/lldb-server/TestLldbGdbServer.py
@@ -667,7 +667,8 @@
# Verify the response length.
p_response = context.get("p_response")
self.assertIsNotNone(p_response)
- self.assertEquals(len(p_response), 2 * int(reg_info["bitsize"]) /
8)
+ if (p_response != 'E15'): # Check if register is available
+ self.assertEquals(len(p_response), 2 *
int(reg_info["bitsize"]) / 8)
# Increment loop
reg_index += 1
Index: test/tools/lldb-server/TestLldbGdbServer.py
===================================================================
--- test/tools/lldb-server/TestLldbGdbServer.py
+++ test/tools/lldb-server/TestLldbGdbServer.py
@@ -667,7 +667,8 @@
# Verify the response length.
p_response = context.get("p_response")
self.assertIsNotNone(p_response)
- self.assertEquals(len(p_response), 2 * int(reg_info["bitsize"]) / 8)
+ if (p_response != 'E15'): # Check if register is available
+ self.assertEquals(len(p_response), 2 * int(reg_info["bitsize"]) / 8)
# Increment loop
reg_index += 1
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