On Fri, Sep 11, 2015 at 01:45:07PM +0100, Will Deacon wrote: > [left the context in the hope that we can make some progress] > > On Wed, Sep 02, 2015 at 10:59:06AM +0100, Will Deacon wrote: > > On Tue, Sep 01, 2015 at 10:45:40PM +0100, Paul E. McKenney wrote: > > > On Tue, Sep 01, 2015 at 08:00:27PM +0100, Will Deacon wrote: > > > > On Fri, Aug 28, 2015 at 04:39:21PM +0100, Peter Zijlstra wrote: > > > > > Yes, the difference between RCpc and RCsc is in the meaning of > > > > > RELEASE + > > > > > ACQUIRE. With RCsc that implies a full memory barrier, with RCpc it > > > > > does > > > > > not. > > > > > > > > We've discussed this before, but for the sake of completeness, I don't > > > > think we're fully RCsc either because we don't order the actual RELEASE > > > > operation again a subsequent ACQUIRE operation: > > > > > > > > P0 > > > > smp_store_release(&x, 1); > > > > foo = smp_load_acquire(&y); > > > > > > > > P1 > > > > smp_store_release(&y, 1); > > > > bar = smp_load_acquire(&x); > > > > > > > > We allow foo == bar == 0, which is prohibited by SC. > > > > > > I certainly hope that no one expects foo == bar == 0 to be prohibited!!! > > > > I just thought it was worth making this point, because it is prohibited > > in SC and I don't want people to think that our RELEASE/ACQUIRE operations > > are SC (even though they happen to be on arm64). > > > > > On the other hand, in this case, foo == bar == 1 will be prohibited: > > > > > > P0 > > > foo = smp_load_acquire(&y); > > > smp_store_release(&x, 1); > > > > > > P1 > > > bar = smp_load_acquire(&x); > > > smp_store_release(&y, 1); > > > > Agreed. > > > > > > However, we *do* enforce ordering on any prior or subsequent accesses > > > > for the code snippet above (the release and acquire combine to give a > > > > full barrier), which makes these primitives well suited to things like > > > > message passing. > > > > > > If I understand your example correctly, neither x86 nor Power implement > > > a full barrier in this case. For example: > > > > > > P0 > > > WRITE_ONCE(a, 1); > > > smp_store_release(b, 1); > > > r1 = smp_load_acquire(c); > > > r2 = READ_ONCE(d); > > > > > > P1 > > > WRITE_ONCE(d, 1); > > > smp_mb(); > > > r3 = READ_ONCE(a); > > > > > > Both x86 and Power can reorder P0 as follows: > > > > > > P0 > > > r1 = smp_load_acquire(c); > > > r2 = READ_ONCE(d); > > > WRITE_ONCE(a, 1); > > > smp_store_release(b, 1); > > > > > > Which clearly shows that the non-SC outcome r2 == 0 && r3 == 0 is allowed. > > > > > > Or am I missing your point here? > > > > I think this example is slightly different. Having the RELEASE/ACQUIRE > > operations being reordered with respect to each other is one thing, but > > I thought we were heading in a direction where they combined to give a > > full barrier with respect to other accesses. In that case, the reordering > > above would be forbidden. > > > > Peter -- if the above reordering can happen on x86, then moving away > > from RCpc is going to be less popular than I hoped... > > Peter, any thoughts? I'm not au fait with the x86 memory model, but what > Paul's saying is worrying.
The herd tool has an x86 mode, which will allow you to double-check my scenario. This tool is described in "Herding Cats: Modelling, Simulation, Testing, and Data-mining for Weak Memory" by Alglave, Marenget, and Tautschnig. The herd tool is available at this git repository: https://github.com/herd/herdtools. Thanx, Paul _______________________________________________ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
