On Wed, May 20, 2015 at 09:17:11PM -0500, Scott Wood wrote:
> From: Jaiprakash Singh <b44...@freescale.com>
>
> IFC IO accressor are set at run time based
> on IFC IP registers endianness.IFC node in
> DTS file contains information about
> endianness.
>
> Signed-off-by: Jaiprakash Singh <b44...@freescale.com>
> Signed-off-by: Scott Wood <scottw...@freescale.com>
> ---
> v5: I'm assuming it's the same as v4, but I didn't send v4, and this
> comes from a versionless [RESEND] that never made it to the mailing list,
> so bumping the version just in case.
Acked-by: Brian Norris <computersforpe...@gmail.com>
Who takes patches for drivers/memory/ again? I can take it via MTD if
no one else steps up.
It's nothing new, but this patch continues the pattern of using a global
pointer to the IFC device structure. Not pretty, but not worth holding
this up over.
Brian
> .../bindings/memory-controllers/fsl/ifc.txt | 3 +
> drivers/memory/fsl_ifc.c | 43 ++--
> drivers/mtd/nand/fsl_ifc_nand.c | 258
> +++++++++++----------
> include/linux/fsl_ifc.h | 50 ++++
> 4 files changed, 213 insertions(+), 141 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/memory-controllers/fsl/ifc.txt
> b/Documentation/devicetree/bindings/memory-controllers/fsl/ifc.txt
> index d5e3704..89427b0 100644
> --- a/Documentation/devicetree/bindings/memory-controllers/fsl/ifc.txt
> +++ b/Documentation/devicetree/bindings/memory-controllers/fsl/ifc.txt
> @@ -18,6 +18,8 @@ Properties:
> interrupt (NAND_EVTER_STAT). If there is only one,
> that interrupt reports both types of event.
>
> +- little-endian : If this property is absent, the big-endian mode will
> + be in use as default for registers.
>
> - ranges : Each range corresponds to a single chipselect, and covers
> the entire access window as configured.
> @@ -34,6 +36,7 @@ Example:
> #size-cells = <1>;
> reg = <0x0 0xffe1e000 0 0x2000>;
> interrupts = <16 2 19 2>;
> + little-endian;
>
> /* NOR, NAND Flashes and CPLD on board */
> ranges = <0x0 0x0 0x0 0xee000000 0x02000000
> diff --git a/drivers/memory/fsl_ifc.c b/drivers/memory/fsl_ifc.c
> index 410c397..e87459f 100644
> --- a/drivers/memory/fsl_ifc.c
> +++ b/drivers/memory/fsl_ifc.c
> @@ -62,7 +62,7 @@ int fsl_ifc_find(phys_addr_t addr_base)
> return -ENODEV;
>
> for (i = 0; i < fsl_ifc_ctrl_dev->banks; i++) {
> - u32 cspr = in_be32(&fsl_ifc_ctrl_dev->regs->cspr_cs[i].cspr);
> + u32 cspr = ifc_in32(&fsl_ifc_ctrl_dev->regs->cspr_cs[i].cspr);
> if (cspr & CSPR_V && (cspr & CSPR_BA) ==
> convert_ifc_address(addr_base))
> return i;
> @@ -79,16 +79,16 @@ static int fsl_ifc_ctrl_init(struct fsl_ifc_ctrl *ctrl)
> /*
> * Clear all the common status and event registers
> */
> - if (in_be32(&ifc->cm_evter_stat) & IFC_CM_EVTER_STAT_CSER)
> - out_be32(&ifc->cm_evter_stat, IFC_CM_EVTER_STAT_CSER);
> + if (ifc_in32(&ifc->cm_evter_stat) & IFC_CM_EVTER_STAT_CSER)
> + ifc_out32(IFC_CM_EVTER_STAT_CSER, &ifc->cm_evter_stat);
>
> /* enable all error and events */
> - out_be32(&ifc->cm_evter_en, IFC_CM_EVTER_EN_CSEREN);
> + ifc_out32(IFC_CM_EVTER_EN_CSEREN, &ifc->cm_evter_en);
>
> /* enable all error and event interrupts */
> - out_be32(&ifc->cm_evter_intr_en, IFC_CM_EVTER_INTR_EN_CSERIREN);
> - out_be32(&ifc->cm_erattr0, 0x0);
> - out_be32(&ifc->cm_erattr1, 0x0);
> + ifc_out32(IFC_CM_EVTER_INTR_EN_CSERIREN, &ifc->cm_evter_intr_en);
> + ifc_out32(0x0, &ifc->cm_erattr0);
> + ifc_out32(0x0, &ifc->cm_erattr1);
>
> return 0;
> }
> @@ -127,9 +127,9 @@ static u32 check_nand_stat(struct fsl_ifc_ctrl *ctrl)
>
> spin_lock_irqsave(&nand_irq_lock, flags);
>
> - stat = in_be32(&ifc->ifc_nand.nand_evter_stat);
> + stat = ifc_in32(&ifc->ifc_nand.nand_evter_stat);
> if (stat) {
> - out_be32(&ifc->ifc_nand.nand_evter_stat, stat);
> + ifc_out32(stat, &ifc->ifc_nand.nand_evter_stat);
> ctrl->nand_stat = stat;
> wake_up(&ctrl->nand_wait);
> }
> @@ -161,16 +161,16 @@ static irqreturn_t fsl_ifc_ctrl_irq(int irqno, void
> *data)
> irqreturn_t ret = IRQ_NONE;
>
> /* read for chip select error */
> - cs_err = in_be32(&ifc->cm_evter_stat);
> + cs_err = ifc_in32(&ifc->cm_evter_stat);
> if (cs_err) {
> dev_err(ctrl->dev, "transaction sent to IFC is not mapped to"
> "any memory bank 0x%08X\n", cs_err);
> /* clear the chip select error */
> - out_be32(&ifc->cm_evter_stat, IFC_CM_EVTER_STAT_CSER);
> + ifc_out32(IFC_CM_EVTER_STAT_CSER, &ifc->cm_evter_stat);
>
> /* read error attribute registers print the error information */
> - status = in_be32(&ifc->cm_erattr0);
> - err_addr = in_be32(&ifc->cm_erattr1);
> + status = ifc_in32(&ifc->cm_erattr0);
> + err_addr = ifc_in32(&ifc->cm_erattr1);
>
> if (status & IFC_CM_ERATTR0_ERTYP_READ)
> dev_err(ctrl->dev, "Read transaction error"
> @@ -231,6 +231,23 @@ static int fsl_ifc_ctrl_probe(struct platform_device
> *dev)
> goto err;
> }
>
> + version = ifc_in32(&fsl_ifc_ctrl_dev->regs->ifc_rev) &
> + FSL_IFC_VERSION_MASK;
> + banks = (version == FSL_IFC_VERSION_1_0_0) ? 4 : 8;
> + dev_info(&dev->dev, "IFC version %d.%d, %d banks\n",
> + version >> 24, (version >> 16) & 0xf, banks);
> +
> + fsl_ifc_ctrl_dev->version = version;
> + fsl_ifc_ctrl_dev->banks = banks;
> +
> + if (of_property_read_bool(dev->dev.of_node, "little-endian")) {
> + fsl_ifc_ctrl_dev->little_endian = true;
> + dev_dbg(&dev->dev, "IFC REGISTERS are LITTLE endian\n");
> + } else {
> + fsl_ifc_ctrl_dev->little_endian = false;
> + dev_dbg(&dev->dev, "IFC REGISTERS are BIG endian\n");
> + }
> +
> version = ioread32be(&fsl_ifc_ctrl_dev->regs->ifc_rev) &
> FSL_IFC_VERSION_MASK;
> banks = (version == FSL_IFC_VERSION_1_0_0) ? 4 : 8;
> diff --git a/drivers/mtd/nand/fsl_ifc_nand.c b/drivers/mtd/nand/fsl_ifc_nand.c
> index 51394e5..a4e27e8 100644
> --- a/drivers/mtd/nand/fsl_ifc_nand.c
> +++ b/drivers/mtd/nand/fsl_ifc_nand.c
> @@ -238,8 +238,8 @@ static void set_addr(struct mtd_info *mtd, int column,
> int page_addr, int oob)
>
> ifc_nand_ctrl->page = page_addr;
> /* Program ROW0/COL0 */
> - iowrite32be(page_addr, &ifc->ifc_nand.row0);
> - iowrite32be((oob ? IFC_NAND_COL_MS : 0) | column, &ifc->ifc_nand.col0);
> + ifc_out32(page_addr, &ifc->ifc_nand.row0);
> + ifc_out32((oob ? IFC_NAND_COL_MS : 0) | column, &ifc->ifc_nand.col0);
>
> buf_num = page_addr & priv->bufnum_mask;
>
> @@ -301,19 +301,19 @@ static void fsl_ifc_run_command(struct mtd_info *mtd)
> int i;
>
> /* set the chip select for NAND Transaction */
> - iowrite32be(priv->bank << IFC_NAND_CSEL_SHIFT,
> - &ifc->ifc_nand.nand_csel);
> + ifc_out32(priv->bank << IFC_NAND_CSEL_SHIFT,
> + &ifc->ifc_nand.nand_csel);
>
> dev_vdbg(priv->dev,
> "%s: fir0=%08x fcr0=%08x\n",
> __func__,
> - ioread32be(&ifc->ifc_nand.nand_fir0),
> - ioread32be(&ifc->ifc_nand.nand_fcr0));
> + ifc_in32(&ifc->ifc_nand.nand_fir0),
> + ifc_in32(&ifc->ifc_nand.nand_fcr0));
>
> ctrl->nand_stat = 0;
>
> /* start read/write seq */
> - iowrite32be(IFC_NAND_SEQ_STRT_FIR_STRT, &ifc->ifc_nand.nandseq_strt);
> + ifc_out32(IFC_NAND_SEQ_STRT_FIR_STRT, &ifc->ifc_nand.nandseq_strt);
>
> /* wait for command complete flag or timeout */
> wait_event_timeout(ctrl->nand_wait, ctrl->nand_stat,
> @@ -336,7 +336,7 @@ static void fsl_ifc_run_command(struct mtd_info *mtd)
> int sector_end = sector + chip->ecc.steps - 1;
>
> for (i = sector / 4; i <= sector_end / 4; i++)
> - eccstat[i] = ioread32be(&ifc->ifc_nand.nand_eccstat[i]);
> + eccstat[i] = ifc_in32(&ifc->ifc_nand.nand_eccstat[i]);
>
> for (i = sector; i <= sector_end; i++) {
> errors = check_read_ecc(mtd, ctrl, eccstat, i);
> @@ -376,33 +376,33 @@ static void fsl_ifc_do_read(struct nand_chip *chip,
>
> /* Program FIR/IFC_NAND_FCR0 for Small/Large page */
> if (mtd->writesize > 512) {
> - iowrite32be((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
> - (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
> - (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
> - (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) |
> - (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP4_SHIFT),
> - &ifc->ifc_nand.nand_fir0);
> - iowrite32be(0x0, &ifc->ifc_nand.nand_fir1);
> -
> - iowrite32be((NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) |
> - (NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT),
> - &ifc->ifc_nand.nand_fcr0);
> + ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
> + (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
> + (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
> + (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) |
> + (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP4_SHIFT),
> + &ifc->ifc_nand.nand_fir0);
> + ifc_out32(0x0, &ifc->ifc_nand.nand_fir1);
> +
> + ifc_out32((NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) |
> + (NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT),
> + &ifc->ifc_nand.nand_fcr0);
> } else {
> - iowrite32be((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
> - (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
> - (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
> - (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP3_SHIFT),
> - &ifc->ifc_nand.nand_fir0);
> - iowrite32be(0x0, &ifc->ifc_nand.nand_fir1);
> + ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
> + (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
> + (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
> + (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP3_SHIFT),
> + &ifc->ifc_nand.nand_fir0);
> + ifc_out32(0x0, &ifc->ifc_nand.nand_fir1);
>
> if (oob)
> - iowrite32be(NAND_CMD_READOOB <<
> - IFC_NAND_FCR0_CMD0_SHIFT,
> - &ifc->ifc_nand.nand_fcr0);
> + ifc_out32(NAND_CMD_READOOB <<
> + IFC_NAND_FCR0_CMD0_SHIFT,
> + &ifc->ifc_nand.nand_fcr0);
> else
> - iowrite32be(NAND_CMD_READ0 <<
> - IFC_NAND_FCR0_CMD0_SHIFT,
> - &ifc->ifc_nand.nand_fcr0);
> + ifc_out32(NAND_CMD_READ0 <<
> + IFC_NAND_FCR0_CMD0_SHIFT,
> + &ifc->ifc_nand.nand_fcr0);
> }
> }
>
> @@ -422,7 +422,7 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd,
> unsigned int command,
> switch (command) {
> /* READ0 read the entire buffer to use hardware ECC. */
> case NAND_CMD_READ0:
> - iowrite32be(0, &ifc->ifc_nand.nand_fbcr);
> + ifc_out32(0, &ifc->ifc_nand.nand_fbcr);
> set_addr(mtd, 0, page_addr, 0);
>
> ifc_nand_ctrl->read_bytes = mtd->writesize + mtd->oobsize;
> @@ -437,7 +437,7 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd,
> unsigned int command,
>
> /* READOOB reads only the OOB because no ECC is performed. */
> case NAND_CMD_READOOB:
> - iowrite32be(mtd->oobsize - column, &ifc->ifc_nand.nand_fbcr);
> + ifc_out32(mtd->oobsize - column, &ifc->ifc_nand.nand_fbcr);
> set_addr(mtd, column, page_addr, 1);
>
> ifc_nand_ctrl->read_bytes = mtd->writesize + mtd->oobsize;
> @@ -453,19 +453,19 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd,
> unsigned int command,
> if (command == NAND_CMD_PARAM)
> timing = IFC_FIR_OP_RBCD;
>
> - iowrite32be((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
> - (IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) |
> - (timing << IFC_NAND_FIR0_OP2_SHIFT),
> - &ifc->ifc_nand.nand_fir0);
> - iowrite32be(command << IFC_NAND_FCR0_CMD0_SHIFT,
> - &ifc->ifc_nand.nand_fcr0);
> - iowrite32be(column, &ifc->ifc_nand.row3);
> + ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
> + (IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) |
> + (timing << IFC_NAND_FIR0_OP2_SHIFT),
> + &ifc->ifc_nand.nand_fir0);
> + ifc_out32(command << IFC_NAND_FCR0_CMD0_SHIFT,
> + &ifc->ifc_nand.nand_fcr0);
> + ifc_out32(column, &ifc->ifc_nand.row3);
>
> /*
> * although currently it's 8 bytes for READID, we always read
> * the maximum 256 bytes(for PARAM)
> */
> - iowrite32be(256, &ifc->ifc_nand.nand_fbcr);
> + ifc_out32(256, &ifc->ifc_nand.nand_fbcr);
> ifc_nand_ctrl->read_bytes = 256;
>
> set_addr(mtd, 0, 0, 0);
> @@ -480,16 +480,16 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd,
> unsigned int command,
>
> /* ERASE2 uses the block and page address from ERASE1 */
> case NAND_CMD_ERASE2:
> - iowrite32be((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
> - (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP1_SHIFT) |
> - (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP2_SHIFT),
> - &ifc->ifc_nand.nand_fir0);
> + ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
> + (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP1_SHIFT) |
> + (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP2_SHIFT),
> + &ifc->ifc_nand.nand_fir0);
>
> - iowrite32be((NAND_CMD_ERASE1 << IFC_NAND_FCR0_CMD0_SHIFT) |
> - (NAND_CMD_ERASE2 << IFC_NAND_FCR0_CMD1_SHIFT),
> - &ifc->ifc_nand.nand_fcr0);
> + ifc_out32((NAND_CMD_ERASE1 << IFC_NAND_FCR0_CMD0_SHIFT) |
> + (NAND_CMD_ERASE2 << IFC_NAND_FCR0_CMD1_SHIFT),
> + &ifc->ifc_nand.nand_fcr0);
>
> - iowrite32be(0, &ifc->ifc_nand.nand_fbcr);
> + ifc_out32(0, &ifc->ifc_nand.nand_fbcr);
> ifc_nand_ctrl->read_bytes = 0;
> fsl_ifc_run_command(mtd);
> return;
> @@ -506,19 +506,18 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd,
> unsigned int command,
> (NAND_CMD_STATUS << IFC_NAND_FCR0_CMD1_SHIFT) |
> (NAND_CMD_PAGEPROG << IFC_NAND_FCR0_CMD2_SHIFT);
>
> - iowrite32be(
> - (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
> - (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
> - (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
> - (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP3_SHIFT) |
> - (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP4_SHIFT),
> - &ifc->ifc_nand.nand_fir0);
> - iowrite32be(
> - (IFC_FIR_OP_CW1 << IFC_NAND_FIR1_OP5_SHIFT) |
> - (IFC_FIR_OP_RDSTAT <<
> - IFC_NAND_FIR1_OP6_SHIFT) |
> - (IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP7_SHIFT),
> - &ifc->ifc_nand.nand_fir1);
> + ifc_out32(
> + (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
> + (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
> + (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
> + (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP3_SHIFT) |
> + (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP4_SHIFT),
> + &ifc->ifc_nand.nand_fir0);
> + ifc_out32(
> + (IFC_FIR_OP_CW1 << IFC_NAND_FIR1_OP5_SHIFT) |
> + (IFC_FIR_OP_RDSTAT << IFC_NAND_FIR1_OP6_SHIFT) |
> + (IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP7_SHIFT),
> + &ifc->ifc_nand.nand_fir1);
> } else {
> nand_fcr0 = ((NAND_CMD_PAGEPROG <<
> IFC_NAND_FCR0_CMD1_SHIFT) |
> @@ -527,20 +526,19 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd,
> unsigned int command,
> (NAND_CMD_STATUS <<
> IFC_NAND_FCR0_CMD3_SHIFT));
>
> - iowrite32be(
> + ifc_out32(
> (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
> (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP1_SHIFT) |
> (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP2_SHIFT) |
> (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP3_SHIFT) |
> (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP4_SHIFT),
> &ifc->ifc_nand.nand_fir0);
> - iowrite32be(
> - (IFC_FIR_OP_CMD1 << IFC_NAND_FIR1_OP5_SHIFT) |
> - (IFC_FIR_OP_CW3 << IFC_NAND_FIR1_OP6_SHIFT) |
> - (IFC_FIR_OP_RDSTAT <<
> - IFC_NAND_FIR1_OP7_SHIFT) |
> - (IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP8_SHIFT),
> - &ifc->ifc_nand.nand_fir1);
> + ifc_out32(
> + (IFC_FIR_OP_CMD1 << IFC_NAND_FIR1_OP5_SHIFT) |
> + (IFC_FIR_OP_CW3 << IFC_NAND_FIR1_OP6_SHIFT) |
> + (IFC_FIR_OP_RDSTAT << IFC_NAND_FIR1_OP7_SHIFT) |
> + (IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP8_SHIFT),
> + &ifc->ifc_nand.nand_fir1);
>
> if (column >= mtd->writesize)
> nand_fcr0 |=
> @@ -555,7 +553,7 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd,
> unsigned int command,
> column -= mtd->writesize;
> ifc_nand_ctrl->oob = 1;
> }
> - iowrite32be(nand_fcr0, &ifc->ifc_nand.nand_fcr0);
> + ifc_out32(nand_fcr0, &ifc->ifc_nand.nand_fcr0);
> set_addr(mtd, column, page_addr, ifc_nand_ctrl->oob);
> return;
> }
> @@ -563,24 +561,26 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd,
> unsigned int command,
> /* PAGEPROG reuses all of the setup from SEQIN and adds the length */
> case NAND_CMD_PAGEPROG: {
> if (ifc_nand_ctrl->oob) {
> - iowrite32be(ifc_nand_ctrl->index -
> - ifc_nand_ctrl->column,
> - &ifc->ifc_nand.nand_fbcr);
> + ifc_out32(ifc_nand_ctrl->index -
> + ifc_nand_ctrl->column,
> + &ifc->ifc_nand.nand_fbcr);
> } else {
> - iowrite32be(0, &ifc->ifc_nand.nand_fbcr);
> + ifc_out32(0, &ifc->ifc_nand.nand_fbcr);
> }
>
> fsl_ifc_run_command(mtd);
> return;
> }
>
> - case NAND_CMD_STATUS:
> - iowrite32be((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
> - (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP1_SHIFT),
> - &ifc->ifc_nand.nand_fir0);
> - iowrite32be(NAND_CMD_STATUS << IFC_NAND_FCR0_CMD0_SHIFT,
> - &ifc->ifc_nand.nand_fcr0);
> - iowrite32be(1, &ifc->ifc_nand.nand_fbcr);
> + case NAND_CMD_STATUS: {
> + void __iomem *addr;
> +
> + ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
> + (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP1_SHIFT),
> + &ifc->ifc_nand.nand_fir0);
> + ifc_out32(NAND_CMD_STATUS << IFC_NAND_FCR0_CMD0_SHIFT,
> + &ifc->ifc_nand.nand_fcr0);
> + ifc_out32(1, &ifc->ifc_nand.nand_fbcr);
> set_addr(mtd, 0, 0, 0);
> ifc_nand_ctrl->read_bytes = 1;
>
> @@ -590,17 +590,19 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd,
> unsigned int command,
> * The chip always seems to report that it is
> * write-protected, even when it is not.
> */
> + addr = ifc_nand_ctrl->addr;
> if (chip->options & NAND_BUSWIDTH_16)
> - setbits16(ifc_nand_ctrl->addr, NAND_STATUS_WP);
> + ifc_out16(ifc_in16(addr) | (NAND_STATUS_WP), addr);
> else
> - setbits8(ifc_nand_ctrl->addr, NAND_STATUS_WP);
> + ifc_out8(ifc_in8(addr) | (NAND_STATUS_WP), addr);
> return;
> + }
>
> case NAND_CMD_RESET:
> - iowrite32be(IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT,
> - &ifc->ifc_nand.nand_fir0);
> - iowrite32be(NAND_CMD_RESET << IFC_NAND_FCR0_CMD0_SHIFT,
> - &ifc->ifc_nand.nand_fcr0);
> + ifc_out32(IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT,
> + &ifc->ifc_nand.nand_fir0);
> + ifc_out32(NAND_CMD_RESET << IFC_NAND_FCR0_CMD0_SHIFT,
> + &ifc->ifc_nand.nand_fcr0);
> fsl_ifc_run_command(mtd);
> return;
>
> @@ -658,7 +660,7 @@ static uint8_t fsl_ifc_read_byte(struct mtd_info *mtd)
> */
> if (ifc_nand_ctrl->index < ifc_nand_ctrl->read_bytes) {
> offset = ifc_nand_ctrl->index++;
> - return in_8(ifc_nand_ctrl->addr + offset);
> + return ifc_in8(ifc_nand_ctrl->addr + offset);
> }
>
> dev_err(priv->dev, "%s: beyond end of buffer\n", __func__);
> @@ -680,7 +682,7 @@ static uint8_t fsl_ifc_read_byte16(struct mtd_info *mtd)
> * next byte.
> */
> if (ifc_nand_ctrl->index < ifc_nand_ctrl->read_bytes) {
> - data = in_be16(ifc_nand_ctrl->addr + ifc_nand_ctrl->index);
> + data = ifc_in16(ifc_nand_ctrl->addr + ifc_nand_ctrl->index);
> ifc_nand_ctrl->index += 2;
> return (uint8_t) data;
> }
> @@ -726,18 +728,18 @@ static int fsl_ifc_wait(struct mtd_info *mtd, struct
> nand_chip *chip)
> u32 nand_fsr;
>
> /* Use READ_STATUS command, but wait for the device to be ready */
> - iowrite32be((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
> - (IFC_FIR_OP_RDSTAT << IFC_NAND_FIR0_OP1_SHIFT),
> - &ifc->ifc_nand.nand_fir0);
> - iowrite32be(NAND_CMD_STATUS << IFC_NAND_FCR0_CMD0_SHIFT,
> - &ifc->ifc_nand.nand_fcr0);
> - iowrite32be(1, &ifc->ifc_nand.nand_fbcr);
> + ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
> + (IFC_FIR_OP_RDSTAT << IFC_NAND_FIR0_OP1_SHIFT),
> + &ifc->ifc_nand.nand_fir0);
> + ifc_out32(NAND_CMD_STATUS << IFC_NAND_FCR0_CMD0_SHIFT,
> + &ifc->ifc_nand.nand_fcr0);
> + ifc_out32(1, &ifc->ifc_nand.nand_fbcr);
> set_addr(mtd, 0, 0, 0);
> ifc_nand_ctrl->read_bytes = 1;
>
> fsl_ifc_run_command(mtd);
>
> - nand_fsr = ioread32be(&ifc->ifc_nand.nand_fsr);
> + nand_fsr = ifc_in32(&ifc->ifc_nand.nand_fsr);
>
> /*
> * The chip always seems to report that it is
> @@ -829,34 +831,34 @@ static void fsl_ifc_sram_init(struct fsl_ifc_mtd *priv)
> uint32_t cs = priv->bank;
>
> /* Save CSOR and CSOR_ext */
> - csor = ioread32be(&ifc->csor_cs[cs].csor);
> - csor_ext = ioread32be(&ifc->csor_cs[cs].csor_ext);
> + csor = ifc_in32(&ifc->csor_cs[cs].csor);
> + csor_ext = ifc_in32(&ifc->csor_cs[cs].csor_ext);
>
> /* chage PageSize 8K and SpareSize 1K*/
> csor_8k = (csor & ~(CSOR_NAND_PGS_MASK)) | 0x0018C000;
> - iowrite32be(csor_8k, &ifc->csor_cs[cs].csor);
> - iowrite32be(0x0000400, &ifc->csor_cs[cs].csor_ext);
> + ifc_out32(csor_8k, &ifc->csor_cs[cs].csor);
> + ifc_out32(0x0000400, &ifc->csor_cs[cs].csor_ext);
>
> /* READID */
> - iowrite32be((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
> - (IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) |
> - (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP2_SHIFT),
> - &ifc->ifc_nand.nand_fir0);
> - iowrite32be(NAND_CMD_READID << IFC_NAND_FCR0_CMD0_SHIFT,
> - &ifc->ifc_nand.nand_fcr0);
> - iowrite32be(0x0, &ifc->ifc_nand.row3);
> + ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
> + (IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) |
> + (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP2_SHIFT),
> + &ifc->ifc_nand.nand_fir0);
> + ifc_out32(NAND_CMD_READID << IFC_NAND_FCR0_CMD0_SHIFT,
> + &ifc->ifc_nand.nand_fcr0);
> + ifc_out32(0x0, &ifc->ifc_nand.row3);
>
> - iowrite32be(0x0, &ifc->ifc_nand.nand_fbcr);
> + ifc_out32(0x0, &ifc->ifc_nand.nand_fbcr);
>
> /* Program ROW0/COL0 */
> - iowrite32be(0x0, &ifc->ifc_nand.row0);
> - iowrite32be(0x0, &ifc->ifc_nand.col0);
> + ifc_out32(0x0, &ifc->ifc_nand.row0);
> + ifc_out32(0x0, &ifc->ifc_nand.col0);
>
> /* set the chip select for NAND Transaction */
> - iowrite32be(cs << IFC_NAND_CSEL_SHIFT, &ifc->ifc_nand.nand_csel);
> + ifc_out32(cs << IFC_NAND_CSEL_SHIFT, &ifc->ifc_nand.nand_csel);
>
> /* start read seq */
> - iowrite32be(IFC_NAND_SEQ_STRT_FIR_STRT, &ifc->ifc_nand.nandseq_strt);
> + ifc_out32(IFC_NAND_SEQ_STRT_FIR_STRT, &ifc->ifc_nand.nandseq_strt);
>
> /* wait for command complete flag or timeout */
> wait_event_timeout(ctrl->nand_wait, ctrl->nand_stat,
> @@ -866,8 +868,8 @@ static void fsl_ifc_sram_init(struct fsl_ifc_mtd *priv)
> printk(KERN_ERR "fsl-ifc: Failed to Initialise SRAM\n");
>
> /* Restore CSOR and CSOR_ext */
> - iowrite32be(csor, &ifc->csor_cs[cs].csor);
> - iowrite32be(csor_ext, &ifc->csor_cs[cs].csor_ext);
> + ifc_out32(csor, &ifc->csor_cs[cs].csor);
> + ifc_out32(csor_ext, &ifc->csor_cs[cs].csor_ext);
> }
>
> static int fsl_ifc_chip_init(struct fsl_ifc_mtd *priv)
> @@ -884,7 +886,7 @@ static int fsl_ifc_chip_init(struct fsl_ifc_mtd *priv)
>
> /* fill in nand_chip structure */
> /* set up function call table */
> - if ((ioread32be(&ifc->cspr_cs[priv->bank].cspr)) & CSPR_PORT_SIZE_16)
> + if ((ifc_in32(&ifc->cspr_cs[priv->bank].cspr)) & CSPR_PORT_SIZE_16)
> chip->read_byte = fsl_ifc_read_byte16;
> else
> chip->read_byte = fsl_ifc_read_byte;
> @@ -898,13 +900,13 @@ static int fsl_ifc_chip_init(struct fsl_ifc_mtd *priv)
> chip->bbt_td = &bbt_main_descr;
> chip->bbt_md = &bbt_mirror_descr;
>
> - iowrite32be(0x0, &ifc->ifc_nand.ncfgr);
> + ifc_out32(0x0, &ifc->ifc_nand.ncfgr);
>
> /* set up nand options */
> chip->bbt_options = NAND_BBT_USE_FLASH;
> chip->options = NAND_NO_SUBPAGE_WRITE;
>
> - if (ioread32be(&ifc->cspr_cs[priv->bank].cspr) & CSPR_PORT_SIZE_16) {
> + if (ifc_in32(&ifc->cspr_cs[priv->bank].cspr) & CSPR_PORT_SIZE_16) {
> chip->read_byte = fsl_ifc_read_byte16;
> chip->options |= NAND_BUSWIDTH_16;
> } else {
> @@ -917,7 +919,7 @@ static int fsl_ifc_chip_init(struct fsl_ifc_mtd *priv)
> chip->ecc.read_page = fsl_ifc_read_page;
> chip->ecc.write_page = fsl_ifc_write_page;
>
> - csor = ioread32be(&ifc->csor_cs[priv->bank].csor);
> + csor = ifc_in32(&ifc->csor_cs[priv->bank].csor);
>
> /* Hardware generates ECC per 512 Bytes */
> chip->ecc.size = 512;
> @@ -1006,7 +1008,7 @@ static int fsl_ifc_chip_remove(struct fsl_ifc_mtd *priv)
> static int match_bank(struct fsl_ifc_regs __iomem *ifc, int bank,
> phys_addr_t addr)
> {
> - u32 cspr = ioread32be(&ifc->cspr_cs[bank].cspr);
> + u32 cspr = ifc_in32(&ifc->cspr_cs[bank].cspr);
>
> if (!(cspr & CSPR_V))
> return 0;
> @@ -1092,16 +1094,16 @@ static int fsl_ifc_nand_probe(struct platform_device
> *dev)
>
> dev_set_drvdata(priv->dev, priv);
>
> - iowrite32be(IFC_NAND_EVTER_EN_OPC_EN |
> - IFC_NAND_EVTER_EN_FTOER_EN |
> - IFC_NAND_EVTER_EN_WPER_EN,
> - &ifc->ifc_nand.nand_evter_en);
> + ifc_out32(IFC_NAND_EVTER_EN_OPC_EN |
> + IFC_NAND_EVTER_EN_FTOER_EN |
> + IFC_NAND_EVTER_EN_WPER_EN,
> + &ifc->ifc_nand.nand_evter_en);
>
> /* enable NAND Machine Interrupts */
> - iowrite32be(IFC_NAND_EVTER_INTR_OPCIR_EN |
> - IFC_NAND_EVTER_INTR_FTOERIR_EN |
> - IFC_NAND_EVTER_INTR_WPERIR_EN,
> - &ifc->ifc_nand.nand_evter_intr_en);
> + ifc_out32(IFC_NAND_EVTER_INTR_OPCIR_EN |
> + IFC_NAND_EVTER_INTR_FTOERIR_EN |
> + IFC_NAND_EVTER_INTR_WPERIR_EN,
> + &ifc->ifc_nand.nand_evter_intr_en);
> priv->mtd.name = kasprintf(GFP_KERNEL, "%llx.flash", (u64)res.start);
> if (!priv->mtd.name) {
> ret = -ENOMEM;
> diff --git a/include/linux/fsl_ifc.h b/include/linux/fsl_ifc.h
> index bf0321e..0023088 100644
> --- a/include/linux/fsl_ifc.h
> +++ b/include/linux/fsl_ifc.h
> @@ -841,9 +841,59 @@ struct fsl_ifc_ctrl {
>
> u32 nand_stat;
> wait_queue_head_t nand_wait;
> + bool little_endian;
> };
>
> extern struct fsl_ifc_ctrl *fsl_ifc_ctrl_dev;
>
> +static inline u32 ifc_in32(void __iomem *addr)
> +{
> + u32 val;
> +
> + if (fsl_ifc_ctrl_dev->little_endian)
> + val = ioread32(addr);
> + else
> + val = ioread32be(addr);
> +
> + return val;
> +}
> +
> +static inline u16 ifc_in16(void __iomem *addr)
> +{
> + u16 val;
> +
> + if (fsl_ifc_ctrl_dev->little_endian)
> + val = ioread16(addr);
> + else
> + val = ioread16be(addr);
> +
> + return val;
> +}
> +
> +static inline u8 ifc_in8(void __iomem *addr)
> +{
> + return ioread8(addr);
> +}
> +
> +static inline void ifc_out32(u32 val, void __iomem *addr)
> +{
> + if (fsl_ifc_ctrl_dev->little_endian)
> + iowrite32(val, addr);
> + else
> + iowrite32be(val, addr);
> +}
> +
> +static inline void ifc_out16(u16 val, void __iomem *addr)
> +{
> + if (fsl_ifc_ctrl_dev->little_endian)
> + iowrite16(val, addr);
> + else
> + iowrite16be(val, addr);
> +}
> +
> +static inline void ifc_out8(u8 val, void __iomem *addr)
> +{
> + iowrite8(val, addr);
> +}
>
> #endif /* __ASM_FSL_IFC_H */
> --
> 2.1.0
>
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