On Thu, 2014-11-27 at 14:50 -0600, Segher Boessenkool wrote: > On Thu, Nov 27, 2014 at 11:41:40AM -0600, Peter Bergner wrote: > > On Thu, 2014-11-27 at 10:08 -0600, Segher Boessenkool wrote: > > > On Wed, Nov 26, 2014 at 05:50:27PM -0600, Peter Bergner wrote: > > > > Nope, you don't get a SIGILL when executing 64-bit instructions in > > > > 32-bit mode, so it'll happily just execute the instruction, doing > > > > a full 64-bit compare. I'm guessing that the upper 32-bits of both > > > > r3 and r4 contain zeros, so we're probably just getting lucky. > > > > > > You will get a SIGILL if you run on 32-bit hardware. > > > > Ha, I completely forgot about 32-bit hardware. Anyway, I looked > > at the ISA, and cmpdi and cmpwi are just extended mnemonics for > > cmpi, with cmpdi setting the L field to 1. Probably on 32-bit > > hardware, the hardware is just ignoring the L bit being set and > > doing a cmpwi for us??? > > Huh. Yes, maybe some implementations do that. > > The good news is that those then compute the correct thing ;-) > > Can QEMU help catch such bugs more reliably?
That's all moot, that piece of code only exist on 64-bit kernels :-) So the only risk here is the very remote and unlikely case where the register might contain 0 in the low 32-bits and some garbage in the top. Cheers, Ben. _______________________________________________ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
