On 06/02/2014 02:18 PM, Anshuman Khandual wrote: > On 06/01/2014 11:48 AM, Michael Neuling wrote: >> > On Fri, 2014-05-30 at 17:40 +0530, Anshuman Khandual wrote: >>> >> This patch enables support for hardware instruction breakpoints on >>> >> POWER8 with >>> >> the help of a new register called CIABR (Completed Instruction Address >>> >> Breakpoint >>> >> Register). With this patch, single hardware instruction breakpoint can >>> >> be added >>> >> and cleared during any active xmon debug session. This hardware based >>> >> instruction >>> >> breakpoint mechanism works correctly along with the existing TRAP based >>> >> instruction >>> >> breakpoints available on xmon. Example usage as follows. >> > >> > Have you actually tried this on a guest? >> > > Yeah on a guest which runs on PVM. > >> > Please also compile with a range of configs. It doesn't compile with >> > ppc64e_defconfig. > Yeah. Need to change the way we get the "plapr_set_ciabr" function from > plpar_wrappers.h > header file. Will add this hunk of code in "xmon.h" header and remove the > CONFIG_PPC64 ifdef > code from the function write_ciabr. > > +#ifdef CONFIG_PPC_BOOK3S_64
"#if defined(CONFIG_PPC_BOOK3S_64) && defined(CONFIG_PPC_SPLPAR)" here actually makes it build on all these configurations listed below. pseries_defconfig ppc64_defconfig ppc64e_defconfig pmac32_defconfig ppc44x_defconfig ppc6xx_defconfig mpc85xx_smp_defconfig mpc85xx_defconfig chroma_defconfig ps3_defconfig celleb_defconfig allnoconfig _______________________________________________ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
