On Mon, 2014-01-06 at 13:27 +0800, wyang wrote: > > On 01/06/2014 11:41 AM, Gavin Hu wrote: > > > Thanks your response. :) > > But that means that these optimitive operations like atomic_add() > > aren't optimitive actully in PPC architecture, right? Becuase they > > can be interrupted by loacl HW interrupts. Theoretically, the ISR > > also can access the atomic gloable variable. > > > > Nope, my understand is that if you wanna sync kernel primitive code > with ISR, you have responsibility to disable local interrupts. > atomic_add does not guarantee to handle such case.
atomic_add() and other atomics do handle that case. Interrupts are not disabled, but there's a stwcx. in the interrupt return code to make sure the reservation gets cleared. -Scott _______________________________________________ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
