On 06/30/2013 11:12:23 PM, Haijun Zhang wrote:
From: "Haijun.Zhang" <haijun.zh...@freescale.com>
Overview of P1020RDB-PD device:
- DDR3 2GB
- NOR flash 64MB
- NAND flash 128MB
- SPI flash 16MB
- I2C EEPROM 256Kb
- eTSEC1 (RGMII PHY) connected to VSC7385 L2 switch
- eTSEC2 (SGMII PHY)
- eTSEC3 (RGMII PHY)
- SDHC
- 2 USB ports
- 4 TDM ports
- PCIe
Signed-off-by: Haijun Zhang <haijun.zh...@freescale.com>
Signed-off-by: Jerry Huang <chang-ming.hu...@freescale.com>
CC: Scott Wood <scottw...@freescale.com>
---
arch/powerpc/boot/dts/p1020rdb-pd.dtsi | 257
++++++++++++++++++++++++++++++
arch/powerpc/boot/dts/p1020rdb-pd_32b.dts | 90 +++++++++++
2 files changed, 347 insertions(+)
create mode 100644 arch/powerpc/boot/dts/p1020rdb-pd.dtsi
create mode 100644 arch/powerpc/boot/dts/p1020rdb-pd_32b.dts
What about 36b?
+ cpld@2,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "cpld";
+ reg = <0x2 0x0 0x20000>;
+ read-only;
+ };
Where does "cpld" as a compatible come from (it's way too vague)? What
is read-only supposed to mean here?
Why do you have #address-cells/#size-cells if there are no child nodes?
-Scott
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