>>> + /* On 8xx, cache control instructions (particularly
>>> + * "dcbst" from flush_dcache_icache) fault as write
>>> + * operation if there is an unpopulated TLB entry
>>> + * for the address in question. To workaround that,
>>> + * we invalidate the TLB here, thus avoiding dcbst
>>> + * misbehaviour.
>>> + */
>>> + /* 8xx doesn't care about PID, size or ind args */
>>> + _tlbil_va(addr, 0, 0, 0);
>>> #endif /* CONFIG_8xx */
>>> +
>>> + if (!pg)
>>> + return pte;
>>> +
>>> + if (!PageReserved(pg)&& !test_bit(PG_arch_1,&pg->flags)) {
>>> flush_dcache_icache_page(pg);
>>> set_bit(PG_arch_1,&pg->flags);
>>> }
>> Rex, do you recall under what specific circumstances the _tlbil_va is
>> needed? Is it possible that it will be caused by a dcbst in other
>> contexts that are not dependent on the state of PG_arch_1?
The 8xx tlbil_va should not be needed in recent 2.6 after I fixed the 8xx TLB
code
to workaround the dcbst bug there instead. See
http://git.kernel.org/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commitdiff;h=0a2ab51ffb8dfdf51402dcfb446629648c96bc78;hp=60e071fee994ff98c37d03a4a7c5a3f8b1e3b8e5
Not sure what release it went into though.
Jocke
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