On Thu, Jul 8, 2010 at 13:24, Josh Boyer <jwbo...@linux.vnet.ibm.com> wrote: > On Thu, Jul 08, 2010 at 11:01:11AM -0500, Lee Nipper wrote: >>On Thu, Jul 8, 2010 at 10:06, Marc Chidester <marcchides...@gmail.com> wrote: >>> It looks like the Rev D version of the 405EX chip without security >>> will be identified as a 405EXr, based on the values in the cpu_specs >>> table. For 405EX/405EXr the pvr_mask is 0xffff0004 with the >>> pvr_value's as 0x12910004 and 0x12910000 respectively. I see that the >>> Rev D PVR value for the 405EX without security is 0x12911473, which >>> would mask out to the EXr value. >>> >>> Is there an algorithm update needed or am I missing something? >> >>With 405EX Rev D, we have noticed that we must reset our board >>one time after the initial powerup to make the PVR read correctly. >> >>See this post: >>http://lists.ozlabs.org/pipermail/linuxppc-dev/2009-December/079099.html > > That is very very weird. Have you seen that behavior on multiple Rev D CPUs > or just one board or? >
Multiple Rev D CPUs. In fact, ALL of the samples we obtained behave this way. > The PVR value should never change, so if you have odd behavior I wonder if the > are silicon bugs in that revision. Did you happen to ask AMCC about it? > Yes, I did. AMCC suggested doing an early one-time s/w reset to make the PVR read "correctly" afterwards. Since we only support one specific 405EX variety, we could do that. However, on a generic u-boot, there is no way to know if a "correct" PVR is read, so that approach is not a solution. I'm wondering if our power on reset circuitry is not entirely correct, and it showed up with the Rev D part. I received no comments on my original post from other users of the 405EX, so I'm thinking it is a possible explanation. Does anyone have a board with a 405EX Rev D ? If so, does the PVR value match your processor chip after power up ? Lee _______________________________________________ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
