Benjamin Herrenschmidt <b...@kernel.crashing.org> wrote on 09/12/2009 09:56:35:
> From: Benjamin Herrenschmidt <b...@kernel.crashing.org>
> To: Joakim Tjernlund <joakim.tjernl...@transmode.se>
> Cc: "linuxppc-...@ozlabs.org" <linuxppc-...@ozlabs.org>, Rex Feany
> <rfe...@mrv.com>, Scott Wood <scottw...@freescale.com>
> Date: 09/12/2009 09:56
> Subject: Re: [PATCH 04/10] 8xx: Always pin kernel instruction TLB
>
> On Wed, 2009-12-09 at 08:39 +0100, Joakim Tjernlund wrote:
> > The later isn't as simple :) I believe the bulk of such code in
> > entry_32.S.
>
> Yeah but it would be useful for hash I suppose if one really wants to
> boot with nobats. Though at least on hash most of the time we have ways
> to recover by mean of MSR:RI being cleared, which your TLB miss code
> doesn't check...
>
> > Anyhow, the config option is still valid as if enabled
> > it will pin several DTLB's too. Scott had some concerns about removing
> > the config option completely so this was the next best thing.
>
> Well, if you want to pin at least one entry, then just remove the #if
> completely but don't leave a #if 1 :-)
As you wish. Here is a new version without the #if 1
This is required for 8xx to work in Linus current tree.
>From 5a4fa5078ba1774b037dbfd88b9c87b74cf76db7 Mon Sep 17 00:00:00 2001
From: Joakim Tjernlund <joakim.tjernl...@transmode.se>
Date: Fri, 13 Nov 2009 00:26:59 +0100
Subject: [PATCH] 8xx: Always pin kernel instruction TLB
Various kernel asm modifies SRR0/SRR1 just before executing
a rfi. If such code crosses a page boundary you risk a TLB miss
which will clobber SRR0/SRR1. Avoid this by always pinning
kernel instruction TLB space.
Signed-off-by: Joakim Tjernlund <joakim.tjernl...@transmode.se>
---
arch/powerpc/kernel/head_8xx.S | 8 ++++----
1 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
index adc5a32..c80e7c5 100644
--- a/arch/powerpc/kernel/head_8xx.S
+++ b/arch/powerpc/kernel/head_8xx.S
@@ -767,12 +767,12 @@ start_here:
*/
initial_mmu:
tlbia /* Invalidate all TLB entries */
-#ifdef CONFIG_PIN_TLB
+/* Always pin the first 8 MB ITLB to prevent ITLB
+ misses while mucking around with SRR0/SRR1 in asm
+*/
lis r8, mi_rs...@h
ori r8, r8, 0x1c00
-#else
- li r8, 0
-#endif
+
mtspr SPRN_MI_CTR, r8 /* Set instruction MMU control */
#ifdef CONFIG_PIN_TLB
--
1.6.4.4
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