Segher Boessenkool wrote: >>>>>>> +/* >>>>>>> + * Each interrupt has a corresponding bit in both >>>>>>> + * the Interrupt Cause (ICR) and Interrupt Mask (IMR) registers. >>>>>>> + * >>>>>>> + * Enabling/disabling an interrupt line involves asserting/clearing >>>>>>> + * the corresponding bit in IMR. ACK'ing a request simply involves >>>>>>> + * asserting the corresponding bit in ICR. >>>>>>> + */ >>>> >>>> I looked it up in YAGCD; it says that _reading_ the ICR reg already >>>> acks all interrupts (and clears the bits), you never write this reg! >>> >>> YAGCD is not always right. You should not take it as _the truth_. >> >> Oh I know. But I have no better source of information. Well I could >> actually test it, that's very easy using OF :-) Let's do that. > > I tested it. It turns out that neither reading or writing this register > does anything; the bits are automatically cleared when the source > deasserts. >
I checked it too on the Nintendo GameCube making the ack a no-op. It turns out that we _need_ to ack the RSW (Reset Switch) interrupt. The other interrupt sources checked (EXI, VI, DI, AI, DSP/ARAM) need no explicit ack. > I didn't test all interrupts, some are harder to generate "on demand" than > others. > Thanks, Albert _______________________________________________ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
