Paul Mackerras wrote:
Avi Kivity writes:
An alternative implementation using 64-bit cmpxchg will recover most of
the costs of hashed spinlocks. I assume most serious 32-bit
architectures have them?
Have a 64-bit cmpxchg, you mean? x86 is the only one I know of, and
it already has an atomic64_t implementation using cmpxchg8b (or
whatever it's called).
Yes (and it is cmpxchg8b). I'm surprised powerpc doesn't have DCAS support.
My thinking is that the 32-bit non-x86 architectures will be mostly
UP, so the overhead is just an interrupt enable/restore. Those that
are SMP I would expect to be small SMP -- mostly just 2 cpus and maybe
a few 4-way systems.
The new Nehalems provide 8 logical threads in a single socket. All
those threads share a cache, and they have cmpxchg8b anyway, so this
won't matter.
--
error compiling committee.c: too many arguments to function
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