Avi Kivity writes: > An alternative implementation using 64-bit cmpxchg will recover most of > the costs of hashed spinlocks. I assume most serious 32-bit > architectures have them?
Have a 64-bit cmpxchg, you mean? x86 is the only one I know of, and it already has an atomic64_t implementation using cmpxchg8b (or whatever it's called). My thinking is that the 32-bit non-x86 architectures will be mostly UP, so the overhead is just an interrupt enable/restore. Those that are SMP I would expect to be small SMP -- mostly just 2 cpus and maybe a few 4-way systems. Paul. _______________________________________________ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
