> > + /* Flush and disable I/D cache. */
> > + __asm__ __volatile__ ("mfspr 3, 1008" ::: "r3");
> > + __asm__ __volatile__ ("ori 5, 5, 0xcc00" ::: "r5");
> > + __asm__ __volatile__ ("ori 4, 3, 0xc00" ::: "r4");
> > + __asm__ __volatile__ ("andc 5, 3, 5" ::: "r5");
>
> Don't do this; instead, have one multi-line asm statement (or better yet,
> just use mfspr()/mtspr()/sync()/isync()).
>
> GCC is perfectly free to trash your registers in between statements.
Also there's already some code around to properly flush & disable the
caches on those processors.
Ben.
_______________________________________________
Linuxppc-dev mailing list
Linuxppc-dev@ozlabs.org
https://ozlabs.org/mailman/listinfo/linuxppc-dev
