Replace the two dw_pcie_find_capability(&pcie->pci, PCI_CAP_ID_EXP) calls in tegra_pcie_dw_host_init() and pex_ep_event_pex_rst_deassert() with dw_pcie_get_pcie_cap() so that the driver-private pcie_cap_base is filled from the same cached value.
tegra_pcie_dw_host_init() is called from .start_link, i.e. after the controller has been initialized, and the PERST# deassert handler runs after the endpoint has been brought out of reset with its clocks and power enabled. The helper therefore performs its single DBI read at the same point as the open coded search, and the private copy keeps working unchanged. Signed-off-by: Hans Zhang <[email protected]> --- drivers/pci/controller/dwc/pcie-tegra194.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index 26e2ac5c58695..9d7ac539aceae 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -906,8 +906,7 @@ static int tegra_pcie_dw_host_init(struct dw_pcie_rp *pp) pp->bridge->ops = &tegra_pci_ops; if (!pcie->pcie_cap_base) - pcie->pcie_cap_base = dw_pcie_find_capability(&pcie->pci, - PCI_CAP_ID_EXP); + pcie->pcie_cap_base = dw_pcie_get_pcie_cap(pci); val = dw_pcie_readl_dbi(pci, PCI_IO_BASE); val &= ~(IO_BASE_IO_DECODE | IO_BASE_IO_DECODE_BIT8); @@ -1890,8 +1889,7 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie) dw_pcie_writel_dbi(pci, GEN3_CTRL, val); } - pcie->pcie_cap_base = dw_pcie_find_capability(&pcie->pci, - PCI_CAP_ID_EXP); + pcie->pcie_cap_base = dw_pcie_get_pcie_cap(pci); /* Clear Slot Clock Configuration bit if SRNS configuration */ if (pcie->enable_srns) { -- 2.43.0
