Convert the dw_pcie_find_capability(pci, PCI_CAP_ID_EXP) users in the Qualcomm host driver to dw_pcie_get_pcie_cap():
qcom_pcie_clear_aspm_l0s() qcom_pcie_set_slot_cap() qcom_pcie_post_init_2_3_3() qcom_pcie_post_init_2_9_0() qcom_pcie_link_up() qcom_pcie_icc_opp_update() Note that the .post_init callbacks of struct qcom_pcie_ops run from qcom_pcie_host_init() before qcom_pcie_clear_aspm_l0s(), so relying on that function to populate the cache would have left the offset uninitialized for them. Doing the lazy lookup inside each function makes the ordering irrelevant: the capability is searched exactly where the register is accessed, i.e. where the open coded dw_pcie_find_capability() call used to be, and every one of these paths runs after qcom_pcie_init_*() has enabled clocks, resets and power. Signed-off-by: Hans Zhang <[email protected]> --- drivers/pci/controller/dwc/pcie-qcom.c | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index d903f10211c23..dfd2d10414ec9 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -379,13 +379,13 @@ static int qcom_pcie_start_link(struct dw_pcie *pci) static void qcom_pcie_clear_aspm_l0s(struct dw_pcie *pci) { struct qcom_pcie *pcie = to_qcom_pcie(pci); - u16 offset; + u8 offset; u32 val; if (!pcie->cfg->no_l0s) return; - offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + offset = dw_pcie_get_pcie_cap(pci); dw_pcie_dbi_ro_wr_en(pci); @@ -398,7 +398,7 @@ static void qcom_pcie_clear_aspm_l0s(struct dw_pcie *pci) static void qcom_pcie_set_slot_cap(struct dw_pcie *pci) { - u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + u8 offset = dw_pcie_get_pcie_cap(pci); u32 val; dw_pcie_dbi_ro_wr_en(pci); @@ -998,7 +998,7 @@ static int qcom_pcie_init_2_3_3(struct qcom_pcie *pcie) static int qcom_pcie_post_init_2_3_3(struct qcom_pcie *pcie) { struct dw_pcie *pci = pcie->pci; - u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + u8 offset = dw_pcie_get_pcie_cap(pci); u32 val; /* Force PHY out of lowest power state */ @@ -1362,7 +1362,7 @@ static int qcom_pcie_init_2_9_0(struct qcom_pcie *pcie) static int qcom_pcie_post_init_2_9_0(struct qcom_pcie *pcie) { struct dw_pcie *pci = pcie->pci; - u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + u8 offset = dw_pcie_get_pcie_cap(pci); u32 val; int i; @@ -1410,7 +1410,7 @@ static int qcom_pcie_post_init_2_9_0(struct qcom_pcie *pcie) static bool qcom_pcie_link_up(struct dw_pcie *pci) { - u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + u8 offset = dw_pcie_get_pcie_cap(pci); u16 val = readw(pci->dbi_base + offset + PCI_EXP_LNKSTA); return val & PCI_EXP_LNKSTA_DLLLA; @@ -1785,14 +1785,15 @@ static int qcom_pcie_icc_init(struct qcom_pcie *pcie) static void qcom_pcie_icc_opp_update(struct qcom_pcie *pcie) { - u32 offset, status, width, speed; + u8 offset; + u32 status, width, speed; struct dw_pcie *pci = pcie->pci; struct dev_pm_opp_key key = {}; unsigned long freq_kbps; struct dev_pm_opp *opp; int ret, freq_mbps; - offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + offset = dw_pcie_get_pcie_cap(pci); status = readw(pci->dbi_base + offset + PCI_EXP_LNKSTA); /* Only update constraints if link is up. */ -- 2.43.0
